QED and Symbolic QED: Dramatic Improvements in Pre-Silicon Verification and Post-Silicon Validation

K Devarajegowda, F Lonsing… - … and Trends® in …, 2024 - nowpublishers.com
Abstract System-on-Chips (SoCs) are an integral part of our lives. The complexity of SoCs
requires sophisticated tools and methods for ensuring functional correctness, especially in …

[PDF][PDF] Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition

S Chattopadhyay, F Lonsing, L Piccolboni… - 2021 Formal Methods …, 2021 - library.oapen.org
Hardware accelerators (HAs) are essential building blocks for fast and energy-efficient
computing systems. Accelerator Quick Error Detection (A-QED) is a recent formal technique …

Verifying High-Level Latency-Insensitive Designs with Formal Model Checking

S Dai, A Klinefelter, H Ren, R Venkatesan… - arXiv preprint arXiv …, 2021 - arxiv.org
Latency-insensitive design mitigates increasing interconnect delay and enables productive
component reuse in complex digital systems. This design style has been adopted in high …

SE3: Sequential Equivalence Checking for Non-Cycle-Accurate Design Transformations

Y Li, G Zhao, Y He, H Zhou - 2023 60th ACM/IEEE Design …, 2023 - ieeexplore.ieee.org
In high-level design explorations, many useful optimizations transform a circuit into another
with different operating cycles for a better trade-off between performance and resource …

[图书][B] Multi-Functional Interfaces for Accelerators

L Piccolboni - 2022 - search.proquest.com
Abstract Heterogeneous System-on-Chip (SoC) architectures combine general-purpose
processors with many accelerators, which are application-specific computing engines. By …

Enhancing Safety and Robustness for Mission-Critical Systems With Formal Methods

Y Li - 2023 - search.proquest.com
Mission-critical systems are those imperative systems whose failures can result in
catastrophic consequences. Traditional techniques, such as manual investigation and …