Circuitry and methods for programming resistive random access memory devices
JL McCollum - US Patent 10,522,224, 2019 - Google Patents
(57) ABSTRACT A method for programming a RelAM cell including a ReRAM device
connected in series with an access transistor includes biasing the ReRAM cell with a …
connected in series with an access transistor includes biasing the ReRAM cell with a …
MRAM reference current
CF Lee, HJ Lin, PH Lee, KF Lin, YC Shih… - US Patent …, 2021 - Google Patents
A reference circuit for generating a reference current includes a plurality of resistive
elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to …
elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to …
Resistive random access memory cell
JL McCollum - US Patent 10,546,633, 2020 - Google Patents
A resistive random access memory cell includes three resis tive random access memory
devices, each resistive random access memory device having an ion source layer and a …
devices, each resistive random access memory device having an ion source layer and a …
Resistive random access memory based multiplexers and field programmable gate arrays
Resistive random access memory (RRAM) based multiplexers and field programmable gate
arrays (FPGAs) are provided. The RRAM-based multiplexers and FPGAs include a 4T1R …
arrays (FPGAs) are provided. The RRAM-based multiplexers and FPGAs include a 4T1R …
Semiconductor storage device
N Yusuke - US Patent 10,468,081, 2019 - Google Patents
A device includes a memory-cell array and a sense-amplifier. A decoder connects a first BL
to the sense amplifier. The decoder includes first and second multiplexers. The first …
to the sense amplifier. The decoder includes first and second multiplexers. The first …
Low leakage ReRAM FPGA configuration cell
JL McCollum, EZ Hamdy - US Patent 10,128,852, 2018 - Google Patents
A low-leakage resistive random access memory cell includes a complementary pair of bit
lines and a switch node. A first ReRAM device is connected to a first one of the bit lines. A p …
lines and a switch node. A first ReRAM device is connected to a first one of the bit lines. A p …
Front to back resistive random-access memory cells
J Greene, F Hawley, J McCollum - US Patent 10,855,286, 2020 - Google Patents
A resistive random-access memory device formed on a semiconductor substrate includes a
first interlayer dielectric formed over the semiconductor substrate and includes a first via. A …
first interlayer dielectric formed over the semiconductor substrate and includes a first via. A …
Circuits and methods for preventing over-programming of ReRAM-based memory cells
V Hecht - US Patent 10,147,485, 2018 - Google Patents
A method for preventing over-programming of resistive random access (ReRAM) based
memory cells in a ReRAM memory array includes applying a programming voltage in a …
memory cells in a ReRAM memory array includes applying a programming voltage in a …
Resistive random-access memory (ReRAM) cell optimized for reset and set currents
L Dagan - US Patent 12,131,777, 2024 - Google Patents
A resistive random-access memory (ReRAM) cell includes a field-effect transistor (FET) and
a resistive element. The FET having a gate port, a drain port, and a source port. The gate …
a resistive element. The FET having a gate port, a drain port, and a source port. The gate …
Magnetic junction memory device and reading method thereof
CK Kim, EJ Lee, JY Kim, TS Kim, JW Joo - US Patent 11,889,703, 2024 - Google Patents
A magnetic junction memory device is provided. The magnetic junction memory device
including a sensing circuit including a sensing node, the sensing node being connected to a …
including a sensing circuit including a sensing node, the sensing node being connected to a …