A 480 mW 2.6 GS/s 10b time-interleaved ADC with 48.5 dB SNDR up to Nyquist in 65 nm CMOS
This paper presents a 64-times interleaved 2.6 GS/s 10b successive-approximation-register
(SAR) ADC in 65 nm CMOS. The ADC combines interleaving hierarchy with an open-loop …
(SAR) ADC in 65 nm CMOS. The ADC combines interleaving hierarchy with an open-loop …
A 480mW 2.6 GS/s 10b 65nm CMOS time-interleaved ADC with 48.5 dB SNDR up to Nyquist
Trends in cable TV reception for data and video require simultaneous capture of many
channels, eg, 16, arbitrary located in the 48-to-1002MHz TV band. The challenges of …
channels, eg, 16, arbitrary located in the 48-to-1002MHz TV band. The challenges of …
A 2.7 mW/channel 48–1000 MHz direct sampling full-band cable receiver
J Wu, G Cusmai, A Wei-Te Chou… - IEEE Journal of Solid …, 2016 - ieeexplore.ieee.org
A direct sampling full-band capture (FBC) receiver for cable and digital TV applications is
presented. It consists of a 0.18 μm BiCMOS low-noise amplifier (LNA) and a 28 nm CMOS …
presented. It consists of a 0.18 μm BiCMOS low-noise amplifier (LNA) and a 28 nm CMOS …
A 130-nm CMOS 100-Hz–6-GHz reconfigurable vector signal analyzer and software-defined receiver
A monolithic 100-Hz-6-GHz reconfigurable vector signal analyzer (VSA) and software-
defined receiver (SDR), following a two-step up-down conversion heterodyne scheme with …
defined receiver (SDR), following a two-step up-down conversion heterodyne scheme with …
A broadband low-power low-noise active balun with second-order distortion cancellation
D Manstretta - IEEE Journal of Solid-State Circuits, 2011 - ieeexplore.ieee.org
This paper presents a broadband single-ended input differential output low noise amplifier
exploiting IM2 cancelling. A linear feedback from the common mode output to the single …
exploiting IM2 cancelling. A linear feedback from the common mode output to the single …
A digital sine-weighted switched-GM mixer for single-clock power-scalable parallel receivers
R Kasri, E Klumperink, P Cathelin… - 2017 IEEE Custom …, 2017 - ieeexplore.ieee.org
This paper presents a mixed A/D architecture for parallel channelized RF receiver
applications. Its power consumption scales with the number of active receivers and hence …
applications. Its power consumption scales with the number of active receivers and hence …
On the performance analysis of energy-efficient upstream scheduling for hybrid fiber-coaxial networks with channel bonding
P Lu, Y Yuan, Z Yang, Z Zhu - IEEE communications letters, 2013 - ieeexplore.ieee.org
We develop a novel QoS-aware energy-efficient upstream traffic scheduling algorithm for
channel-bonding cable modems (CMs) in hybrid fiber-coaxial (HFC) networks. Based on …
channel-bonding cable modems (CMs) in hybrid fiber-coaxial (HFC) networks. Based on …
A direct sampling multi-channel receiver for DOCSIS 3.0 in 65nm CMOS
This paper presents a fully integrated direct sampling receiver for DOCSIS 3.0, consisting of
a time-interleaved ADC, a digital multi-channel selection filter, and a PLL. The receiver can …
a time-interleaved ADC, a digital multi-channel selection filter, and a PLL. The receiver can …
An embedded 65 nm CMOS baseband IQ 48 MHz-1 GHz dual tuner for DOCSIS 3.0
F Gatta, BJJ Gomez, Y Shin, T Hayashi… - IEEE …, 2010 - ieeexplore.ieee.org
An embedded CMOS digital dual tuner for DOCSIS 3.0 and set-top box applications is
presented. The dual tuner down-converts a total of ten 6 MHz Annex B channels or eight 8 …
presented. The dual tuner down-converts a total of ten 6 MHz Annex B channels or eight 8 …
A wideband CMOS VGLNA based on single-to-differential stage and resistive attenuator for TV tuners
K Han, X Tan, Z Tang, H Min - Journal of semiconductors, 2011 - iopscience.iop.org
A wideband CMOS variable gain low noise amplifier (VGLNA) based on a single-to-
differential (S2D) stage and resistive attenuator is presented for TV tuner applications …
differential (S2D) stage and resistive attenuator is presented for TV tuner applications …