Mathematical framework of tetramorphic MWCNT configuration for VLSI interconnect

AB Amin, MS Ullah - IEEE Transactions on Nanotechnology, 2020 - ieeexplore.ieee.org
Having a 1D material like Multiwall Carbon Nanotube (MWCNT) as a potential candidate for
high speed Very Large Scale Integration (VLSI) interconnect creates a good scope to reduce …

Structure fortification of mixed CNT bundle interconnects for nano integrated circuits using constraint-based particle swarm optimization

T Pathade, Y Agrawal, R Parekh… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
The emerging VLSI technology and simultaneously highly dense packaging of devices and
interconnects in nano-scale chips have prosperously enabled realization of system-on-chip …

A literature review on next generation graphene interconnects

N Patel, Y Agrawal - Journal of Circuits, Systems and Computers, 2019 - World Scientific
The state-of-the-art development and subsequent miniaturization of technologies in e-
systems such as computers and digital communication systems have led to densely and …

Emerging interconnects: a state-of-the-art review and emerging solutions

SM Turkane, AK Kureshi - International Journal of Electronics, 2017 - Taylor & Francis
Aluminium was a primary material for interconnection in integrated circuits (ICs) since their
inception. Later, copper was introduced as interconnect material which has better metallic …

Evaluation and reduction of signal integrity issues in multiwalled carbon nanotube on-chip VLSI interconnects

R Mudavath, BR Naik, JP Raj - ECS Journal of Solid State …, 2021 - iopscience.iop.org
Due to advancements in device scaling in very-large-scale integration (VLSI) technology,
signal integrity (SI) issues play a major role to determining the performance of on-chip …

Pragmatic structure optimization: Achieving optimal crosstalk delay and gate oxide reliability of randomly mixed CNT bundle interconnects

R Sharma, MK Rai, R Khanna - Micro and Nanostructures, 2024 - Elsevier
This study explores the potential of randomly mixed carbon nanotube bundle (RMCB) as a
viable on-chip interconnect. Achieving high-quality carbon nanotubes (CNTs) with uniform …

Optimized buffer insertion for efficient interconnects designs

A Khursheed, K Khare - International Journal of Numerical …, 2020 - Wiley Online Library
This typescript focuses on unraveling the functional performance deterioration issues related
to conventional Cu on‐chip nanointerconnecting wires; mainly occurred due to the shrinking …

Crosstalk analysis of dielectric inserted side contact multilayer graphene nanoribbon interconnects for ternary logic system using unconditionally stable FDTD model

G Deepthi, M Tatineni - Microelectronics Journal, 2023 - Elsevier
In the present work, for examining the performance of dielectric inserted side contact
multilayer graphene nano ribbon (DSMLGNR), a novel Unconditionally Stable Finite …

A prominent unified crosstalk model for linear and sub-threshold regions in mixed CNT bundle interconnects

MG Kumar, Y Agrawal, VR Kumar, R Chandel - Microelectronics Journal, 2021 - Elsevier
With the feasibility to scale the devices and interconnects in highly sophisticated VLSI
technology, the demand for high-speed and low-power e-applications have also …

Modelling and analysis of randomly distributed optimised structure of mixed CNT bundle interconnects-impact on crosstalk induced delay

G Mitra, S Kamboj, MK Rai - Multimedia Tools and Applications, 2024 - Springer
Modern VLSI devices are manufactured using deep submicron technology. On-chip
interconnects represent a major performance bottleneck for high-speed VLSI architectures …