The present disclosure provides a semiconductor package, including a first semiconductor
structure, a first bonding dielectric over the first semiconductor structure and surrounding a …

(57) ABSTRACT A semiconductor package includes a first semiconductor device, a second
semiconductor device vertically positioned above the first semiconductor device, and a …

An apparatus includes a first tier, a second tier and a memory. The second tier is vertically
stacked on the first tier. The memory includes a column of memory bit cells. A first portion of …

Semiconductor structures and methods reduce contact resistance, while retaining cost
effectiveness for integration into the process flow by introducing a heavily-doped contact …

(57) ABSTRACT A semiconductor package includes a first semiconductor element, an
insulating layer, and a second semiconductor element. The first semiconductor element …

A method includes polishing a semiconductor substrate of a first die to reveal first through-
vias that extend into the semiconductor substrate, forming a dielectric layer on the …

702/108 8, 405, 442 B2 3/2013 Chen 8, 436, 671 B2 5/2013 Chern et al. 8, 448, 100 B1
5/2013 Lin et al. 8, 610, 488 B2 12/2013 Yu et al. 8, 625, 240 B2 1/2014 Chung et al. 8, 631 …

An IC degradation sensor is disclosed. The IC degradation management sensor includes an
odd number of first logic gates electrically connected in a ring oscillator configura tion, each …

US9460848B2 - Antenna for inter-chip wireless power transmission - Google Patents
US9460848B2 - Antenna for inter-chip wireless power transmission - Google Patents Antenna for …

(57) ABSTRACT A device comprises a first die; and a second die stacked below the first die
with interconnections between the first die and the second die. A least one of the first die or …