In one embodiment, a processor includes a plurality of cores and a power controller
including a first logic, responsive to a determination that the processor resided in a forced …

One embodiment provides for a general-purpose graphics processing unit comprising a
processing array including multiple compute blocks, each compute block including multiple …

The present disclosure provides a new and innovative system and methods for dynamic halt-
polling control. In an example, a system includes a memory, one or more physical …

An IC in which a power state of a circuit in one power domain is managed based at least in
part on a power state of a circuit in another power domain is disclosed. In one embodiment …

In an embodiment, an apparatus includes a cache memory and a control circuit. The control
circuit may be configured to pre-fetch and store a first quantity of instruction data in response …

A method for managing a central processing unit (CPU) and related products are provided.
The method includes the follows. A first prediction condition and a second prediction …

A method for managing a central processing unit and related products are provided. The
method includes the follows. A first prediction condition and a second prediction condition …

In a memory controller, a prefetch indication can be sent to memory to prepare the memory
for a potential future read or write. Statistics can be used to select when such a prefetch …

An IC in which a power state of a circuit in one power domain is managed based at least in
part on a power state of a circuit in another power domain is disclosed. In one embodiment …

Processors may include cache circuitry that is a significant source of power consumption. A
cache is going to be placed into a lower power mode. Based at least in part on this …