Reflections on 10 years of FloPoCo

F de Dinechin - 2019 IEEE 26th Symposium on Computer …, 2019 - ieeexplore.ieee.org
The FloPoCo open-source arithmetic core generator project started modestly in 2008 with a
few parametric floating point cores. It has since then evolved to become a framework for …

A twofold lookup table architecture for efficient approximation of activation functions

Y Xie, ANJ Raj, Z Hu, S Huang, Z Fan… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
In this article, we propose a novel approach to reduce hardware resource consumption
when neural networks (NNs) are deployed on field-programmable gate array (FPGA) …

Next generation arithmetic for edge computing

A Guntoro, C De La Parra, F Merchant… - … , Automation & Test …, 2020 - ieeexplore.ieee.org
Arithmetic is a key component and is ubiquitous in today's digital world, ranging from
embedded to high-performance computing systems. With machine learning at the fore in a …

Minimizing coefficients wordlength for piecewise-polynomial hardware function evaluation with exact or faithful rounding

D De Caro, E Napoli, D Esposito… - … on Circuits and …, 2017 - ieeexplore.ieee.org
Piecewise polynomial interpolation is a well-established technique for hardware function
evaluation. The paper describes a novel technique to minimize polynomial coefficients …

Hierarchical multipartite function evaluation

SF Hsiao, CS Wen, YH Chen… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
Function evaluation is an important arithmetic computation in many signal processing
applications, such as special function units in modern graphics processing units (GPUs) …

Dual-channel multiplier for piecewise-polynomial function evaluation for low-power 3-D graphics

DM Ellaithy, MA El-Moursy, A Zaki… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
A dual-channel multiplier (DCM) for energy efficient second-order piecewise-polynomial
function evaluation for 3-D graphics applications is presented in this paper. The …

A single-source C++ 20 HLS flow for function evaluation on FPGA and beyond.

L Forget, G Harnisch, R Keryell… - Proceedings of the 12th …, 2022 - dl.acm.org
This paper presents a framework to reuse the intelligence of RTL generators in a single-
source HLS setting. This framework is illustrated by a C++ fixed-point library to generate …

SimBU: Self-Similarity-Based Hybrid Binary-Unary Computing for Nonlinear Functions

A Khataei, G Singh, K Bazargan - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
Unary computing is a relatively new method for implementing arbitrary nonlinear functions
that uses unpacked, thermometer number encoding, enabling much lower hardware costs …

Using integer linear programming for correctly rounded multipartite architectures

O Desrentes, F de Dinechin - 2022 International Conference on …, 2022 - ieeexplore.ieee.org
This article introduces several improvements to the multipartite method, a generic technique
for the hardware implementation of numerical functions. A multipartite architecture replaces …

CompressedLUT: An Open Source Tool for Lossless Compression of Lookup Tables for Function Evaluation and Beyond

A Khataei, K Bazargan - Proceedings of the 2024 ACM/SIGDA …, 2024 - dl.acm.org
Lookup tables are widely used in hardware to store arrays of constant values. For instance,
complex mathematical functions in hardware are typically implemented through table-based …