Execution pipeline data forwarding

G Govindu, P Gupta, S Pitkethly, GJ Rozas - US Patent 9,569,214, 2017 - Google Patents
In one embodiment, in an execution pipeline having a plurality of execution subunits, a
method of using a bypass network to directly forward data from a producing execution …

Systems and methods for move elimination with bypass multiple instantiation table

J Anderson - US Patent 9,256,433, 2016 - Google Patents
Abstract Systems and methods for move operation elimination with bypass Multiple
Instantiation Table (MIT) logic. An example processing system may comprise a first data …

Checkpointed buffer for re-entry from runahead

GJ Rozas, P Serris, B Hoyt, S Ramakrishnan… - US Patent …, 2018 - Google Patents
Embodiments related to re-dispatching an instruction selected for re-execution from a buffer
upon a microprocessor re-entering a particular execution location after runahead are …

Physical register table for eliminating move instructions

JD Combs, VR Madduri - US Patent 10,417,001, 2019 - Google Patents
Embodiments of an invention for a physical register table for eliminating move instructions
are disclosed. In one embodiment, a processor includes a physical register file, a register …

Register allocation to threads

FL Rawson III, WE Speight, L Zhang - US Patent 9,501,285, 2016 - Google Patents
A method, system, and computer usable program product for improved register allocation in
a simultaneous multithreaded processor. A determination is made that a thread of an …

Translation address cache for a microprocessor

R Segelken, A Klaiber, N Tuck, D Dunn - US Patent 10,146,545, 2018 - Google Patents
Embodiments related to fetching instructions and alternate versions achieving the same
functionality as the instructions from an instruction cache included in a microprocessor are …

Branching to alternate code based on runahead determination

R Kumar, G Rozas, M Ekman, L Spracklen - US Patent 9,582,280, 2017 - Google Patents
The description covers a system and method for operating a micro-processing system
having a runahead mode of opera tion. In one implementation, the method includes …

Managing potentially invalid results during runahead

B Holmer, GJ Rozas, A Klaiber, J Van Zoeren… - US Patent …, 2017 - Google Patents
Embodiments related to managing potentially invalid results generated/obtained by a
microprocessor during runahead are provided. In one example, a method for operating a …

Translation lookaside buffer entry systems and methods

A Klaiber, GJ Rozas - US Patent 9,547,602, 2017 - Google Patents
Presented systems and methods can facilitate efficient information storage and tracking
operations, including translation look aside buffer operations. In one embodiment, the …

Speculative permission acquisition for shared memory

J Van Zoeren, A Klaiber, GJ Rozas, P Serris - US Patent 9,645,929, 2017 - Google Patents
In a processor, a method for speculative permission acquisition for access to a shared
memory. The method includes receiving a store from a processor core to modify a shared …