A deep understanding of how to reduce flicker phase noise (PN) in oscillators is critical in
supporting ultra-low PN frequency generation for the advanced communications and other …

The mid-rise time-to-digital converter (TDC), eg, a binary (bang-bang) phase detector and
other few-bit TDCs, is commonly used as the phase detector (PD) in a digital phase locked …

This work presents a 6-GHz low-jitter and high figure-of-merit (FoM) fractional-phase-locked
loop (PLL). It uses a digital-to-time converter (DTC)-based sampling PLL architecture. To …

As new applications impose jitter values in the range of a few tens of femtoseconds, the
design of phase-locked loops faces daunting challenges. This paper derives basic relations …

This article presents a fractional-N frequency synthesizer architecture that is able to
overcome the limitations of conventional bang-bang phase-locked loops. A digital …

This article presents a fractional-N sampling type-I phase-locked loop (PLL). To overcome
the impairments of a conventional type-I PLL, namely the frequency-tuning-dependent time …

This article describes an integer-phase-locked loop (PLL) that incorporates a phase detector
sampling both the rising and falling edges of the reference clock. The circuit also uses a new …

A local oscillator (LO) for 5G new radio requires sub-100fs rms jitter to support 64-OAM and
2\times2 MIMO under non-ideal channel conditions 1. Although fractional-N phase-locked …

In this work, an ultra-low-jitter wideband cascaded local oscillation (LO) generator for 5G
frequency range 1 (FR1) is presented. Using the phase-rotating divider (PRD) of the 2nd …

This article proposes a fractional-N digital phase-locked loop (DPLL) that achieves a 265-
μW ultra-lowpower operation. The proposed switching feedback can seamlessly change the …