A 28-nm 75-fsrms Analog Fractional- Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle …
W Wu, CW Yao, K Godbole, R Ni… - IEEE Journal of Solid …, 2019 - ieeexplore.ieee.org
An analog fractional-sampling phase-locked loop (PLL) is presented. It achieves 75-fs rms
jitter, integrated from 10 kHz to 10 MHz, and a− 249.7-dB figure of merit (FoM) at the …
jitter, integrated from 10 kHz to 10 MHz, and a− 249.7-dB figure of merit (FoM) at the …
A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO
W Wu, CW Yao, C Guo, PY Chiang… - IEEE Journal of Solid …, 2021 - ieeexplore.ieee.org
This work presents a 6-GHz low-jitter and high figure-of-merit (FoM) fractional-phase-locked
loop (PLL). It uses a digital-to-time converter (DTC)-based sampling PLL architecture. To …
loop (PLL). It uses a digital-to-time converter (DTC)-based sampling PLL architecture. To …
An mm-wave synthesizer with robust locking reference-sampling PLL and wide-range injection-locked VCO
In this article, a two-stage millimeter (mm)-wave frequency synthesizer with low in-band
noise and robust locking reference-sampling techniques is presented. Using a two-stage …
noise and robust locking reference-sampling techniques is presented. Using a two-stage …
Low-jitter frequency generation techniques for 5G communication: A tutorial
W Wu - IEEE Solid-State Circuits Magazine, 2021 - ieeexplore.ieee.org
5G is the latest global wireless standard, known as the fifth generation of cellular mobile
communication technology. Compared to 4G LTE, 5G increases peak data rates and …
communication technology. Compared to 4G LTE, 5G increases peak data rates and …
Low-power and low-noise millimeter-wave SSPLL with subsampling lock detector for automatic dividerless frequency acquisition
An 8.8-mW, low-noise, 40.5-GHz frequency synthesizer is proposed. The synthesizer system
consists of a subsampling phase-locked loop (SSPLL) with 100-MHz crystal reference, a …
consists of a subsampling phase-locked loop (SSPLL) with 100-MHz crystal reference, a …
A 14-nm 0.14-psrms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration
CW Yao, R Ni, C Lau, W Wu, K Godbole… - IEEE Journal of Solid …, 2017 - ieeexplore.ieee.org
A digital fractional-N phase-locked loop (PLL) is presented. It achieves 137-and 142-fs rms
jitter integrating from 10 kHz to 10 MHz and from 1 kHz to 10 MHz, respectively. With a …
jitter integrating from 10 kHz to 10 MHz and from 1 kHz to 10 MHz, respectively. With a …
A Very Low Phase-Noise Transformer-Coupled Oscillator and PLL for 5G Communications in 0.12 m SiGe BiCMOS
E Wagner, O Shana'a… - IEEE transactions on …, 2019 - ieeexplore.ieee.org
This article presents a 9.9-12.45 GHz voltage-controlled oscillator (VCO) designed in 0.12
μm SiGe BiCMOS with a focus on achieving the lowest possible phase noise using only a …
μm SiGe BiCMOS with a focus on achieving the lowest possible phase noise using only a …
An ultra-low-jitter, mmW-band frequency synthesizer based on digital subsampling PLL using optimally spaced voltage comparators
This article presents a cascaded architecture of a frequency synthesizer to generate ultra-
low-jitter output signals in a millimeter-wave (mmW) frequency band from 28 to 31 GHz. The …
low-jitter output signals in a millimeter-wave (mmW) frequency band from 28 to 31 GHz. The …
Reference oversampling PLL achieving− 256-dB FoM and− 78-dBc reference spur
This article presents a low jitter, low power, low reference spur LC oscillator-based reference
oversampling digital phase locked loop (OSPLL). The proposed reference oversampling …
oversampling digital phase locked loop (OSPLL). The proposed reference oversampling …
A 20.7–43.8-GHz low power reconfigurable× 2/× 3 frequency multiplier for multiple 5G-mm-wave bands
A reconfigurable injection-locked frequency multiplier (RE-ILFM) with both frequency
doubler mode (DM) and tripler mode (TM) is proposed to increase both the operation …
doubler mode (DM) and tripler mode (TM) is proposed to increase both the operation …