[图书][B] Handbook of signal processing systems
In this new edition of the Handbook of Signal Processing Systems, many of the chapters
from the previous editions have been updated, and several new chapters have been added …
from the previous editions have been updated, and several new chapters have been added …
Software defined radio architecture survey for cognitive testbeds
In this paper we present a survey of existing prototypes dedicated to software defined radio.
We propose a classification related to the architectural organization of the prototypes and …
We propose a classification related to the architectural organization of the prototypes and …
Coarse-grained reconfigurable array architectures
BD Sutter, P Raghavan, A Lambrechts - Handbook of signal processing …, 2019 - Springer
Abstract Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same
inner loops that benefit from the high instruction-level parallelism (ILP) support in very long …
inner loops that benefit from the high instruction-level parallelism (ILP) support in very long …
Tile-based processor architecture model for high-efficiency embedded homogeneous multicore platforms
P Manet, B Rousseau - US Patent 9,275,002, 2016 - Google Patents
The present invention relates to a processor which comprises processing elements that
execute instructions in parallel and are connected together with point-to-point …
execute instructions in parallel and are connected together with point-to-point …
A 2-mm 0.1–5 GHz Software-Defined Radio Receiver in 45-nm Digital CMOS
A software-defined radio (SDR) should theoretically receive any modulated frequency
channel in the (un) licensed spectrum, and guarantee top performance with energy savings …
channel in the (un) licensed spectrum, and guarantee top performance with energy savings …
Memory-aware loop mapping on coarse-grained reconfigurable architectures
The coarse-grained reconfigurable architectures (CGRAs) are a promising class of
architectures with the advantages of high performance and high power efficiency. The …
architectures with the advantages of high performance and high power efficiency. The …
High throughput data mapping for coarse-grained reconfigurable architectures
Y Kim, J Lee, A Shrivastava, JW Yoon… - … on Computer-Aided …, 2011 - ieeexplore.ieee.org
Coarse-grained reconfigurable arrays (CGRAs) are a very promising platform, providing
both up to 10–100 MOps/mW of power efficiency and software programmability. However …
both up to 10–100 MOps/mW of power efficiency and software programmability. However …
A 200Mbps+ 2.14 nJ/b digital baseband multi processor system-on-chip for SDRs
V Derudder, B Bougard, A Couvreur… - 2009 Symposium on …, 2009 - ieeexplore.ieee.org
This paper describes the implementation of an energy-efficient digital SDR baseband
platform. The multi processor system-on-chip (MPSOC) is implemented in 90nm CMOS …
platform. The multi processor system-on-chip (MPSOC) is implemented in 90nm CMOS …
Improving nested loop pipelining on coarse-grained reconfigurable architectures
Coarse-grained reconfigurable architecture (CGRA) is a promising architecture with high
performance, high power efficiency, and attraction of flexibility. The computation-intensive …
performance, high power efficiency, and attraction of flexibility. The computation-intensive …
CIACP: A correlation-and iteration-aware cache partitioning mechanism to improve performance of multiple coarse-grained reconfigurable arrays
Multiple coarse-grained reconfigurable arrays (CGRA), which are organized in parallel or
pipeline to complete applications, have become a productive solution to balance the …
pipeline to complete applications, have become a productive solution to balance the …