Designing directory cache coherence protocols is complicated because coherence
transactions are not atomic in modern multicore processors. A coherence transaction …

We present HieraGen, a new tool for automatically generating hierarchical cache coherence
protocols. HieraGen's inputs are the simple, atomic, stable state protocols for each level of …

Multi-core platforms are becoming primary compute platforms for real-time systems such as
avionics and autonomous vehicles. This adoption is primarily driven by the increasing …

We present SYNTHIA, an open and automated tool for synthesizing predictable and high-
performance snooping bus-based cache coherence protocols for multi-core processors in …

Cache coherence protocols are often specified using only stable states and atomic
transactions for a single cache hierarchy level. Designing highly-concurrent, hierarchical …

Predictable hardware cache coherence is a viable shared data communication mechanism
between cores for multicore real-time platforms. Prior works have established that …

By now we have hopefully convinced you that consistency models and cache coherence
protocols are complex and subtle. In this chapter we discuss methods for rigorously …