Well-designed circuits are one key ldquoinsulatingrdquo layer between the increasingly
unruly behavior of scaled complementary metal-oxide-semiconductor devices and the …

We present here a report produced by a workshop on 'Addressing failures in exascale
computing'held in Park City, Utah, 4–11 August 2012. The charter of this workshop was to …

Due to their growing popularity and computational cost, deep neural networks (DNNs) are
being targeted for hardware acceleration. A popular architecture for DNN acceleration …

As machine learning (ML) becomes pervasive in high performance computing, ML has
found its way into safety-critical domains (eg, autonomous vehicles). Thus the reliability of …

With the continuous downscaling of CMOS technologies, the reliability has become a major
bottleneck in the evolution of the next generation systems. Technology trends such as …

As the process feature size continues to scale down, the susceptibility of logic circuits to
radiation induced error has increased. This trend has led to the increase in sensitivity of …

Today, soft errors are one of the major design technology challenges at and beyond the
22nm technology nodes. This article introduces the soft error problem from the perspective …

Neutron-and proton-induced single-event upset cross sections of D-and DICE-Flip/Flops are
analyzed for designs implemented in a 40 nm bulk technology node. Neutron and proton …

With each technology node shrink, a silicon chip becomes more susceptible to soft errors.
The susceptibility further increases as the voltage is scaled down to save energy. Based on …

Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip:
The Next Generation of System-on-Chip Integration examines the current issues restricting …