LC resonant clock is a viable option for low power on-chip clock distributions. A major
limiting factor to its implementation is the large area overhead due to the use of conventional …

High-performance clock distribution has been a challenge for nearly three decades. During
this time, clock synthesis tools and algorithms have strove to address a myriad of important …

Power-performance constraints have been the key driving force that motivated the
microprocessor industry to bring unique design techniques in the past two decades. The …

LC resonant clock is an attracting option for low power on-chip clock distribution designs.
However, a major limiting factor to its implementation is the large area overhead due to the …

Clock networks in high-performance designs are extremely power hungry. One potential
method for reducing the power consumption is to use distributed LC tanks in which energy is …

In order to eliminate the limitation of a narrow frequency range of conventional resonant
clocking, intermittent resonant clocking (IRC) is proposed for near/sub-threshold logic …

A physical design methodology is presented to synchronize digital application specific
integrated circuit (ASIC) designs by a resonant rotary clock network. One novelty of the …

On-chip low skew clock distribution driving large load capacitances can consume as much
as 70% of the total dynamic power that is lost as heat, resulting in high cooling costs. To …

Adiabatic complementary metal–oxide–semiconductor (CMOS) circuits have been proposed
as a low‐power option for CMOS systems‐on‐a‐chip (SoCs) but have not gained popularity …

Through-silicon-vias (TSVs) are the enabling technique for three-dimensional integrated
circuits (3D ICs). However, their large area significantly reduces the benefits that can be …