Increasing interests in Bit-serial SIMD Processing-Using-DRAM (PUD) architectures amplify
the needs for a compiler to automate code generation, credited to their ultra-wide SIMD …

Racetrack memory (RM) techniques have become promising solutions to resolve the
memory wall issue as they increase memory density, reduce energy consumption and are …

There is a growing call for greater amounts of increasingly agile computational power for
edge and cloud infrastructure to serve the computationally complex needs of ubiquitous …

Edge computing is a popular paradigm for accelerating light-to medium-weight machine
learning algorithms initiated from mobile devices without requiring the long communication …

Big data processing has exposed the limits of compute-centric hardware acceleration due to
the memory-to-processor bandwidth bottleneck. Consequently, there has been a shift …

Computing-in-memory (CIM) promises to alleviate the Von Neumann bottleneck and
accelerate data-intensive applications. Depending on the underlying technology and …

Domain-wall memory (DWM) has SRAM class access performance, low energy, high
endurance, high density, and CMOS compatibility. Recently, shift reliability and processing …

Convolutional neural networks (CNNs) have become a ubiquitous algorithm with growing
applications in mobile and edge settings. We describe a compute-in-memory (CIM) …

In-memory processing is becoming a popular method to alleviate the memory bottleneck of
the von Neumann computing model. With the goal of improving both latency and energy cost …

The current-driven motion of magnetic domain walls (DWs) is the working principle of
magnetic racetrack memories. In this type of spintronic technology, high current densities are …