Oversampling ADC: A Review of Recent Design Trends

A Verreault, PV Cicek, A Robichaud - IEEE Access, 2024 - ieeexplore.ieee.org
Oversampling analog-to-digital converters (ADC) serve as the backbone of high-
performance, high-precision data interfaces, owing to their remarkable ability to filter out …

Revisiting the frontiers of analog and mixed-signal integrated circuits architectures and techniques towards the future internet of everything (IoE) applications

RP Martins, PI Mak, SW Sin, MK Law… - … and Trends® in …, 2021 - nowpublishers.com
Abstract People-to-people (P2P) technology-assisted interconnections, embedded in a
global environment, will be at the core of 21st century communications and will command …

An 8.5 ps resolution, cyclic Vernier TDC using a stage-gated ring oscillator and DWA-based dynamic element matching in 28 nm CMOS

VN Nguyen, XT Pham, JW Lee - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
Herein, we present a cyclic Vernier time-to-digital converter (TDC) using a stage-gated ring
oscillator (SGRO) and data-weighted averaging (DWA) dynamic element matching (DEM) …

A Robust Hybrid CT/DT 0-2 MASH DSM with Passive Noise-Shaping SAR ADC

K Li, SW Sin, L Qi, W Zhao, G Wang… - … Symposium on Circuits …, 2022 - ieeexplore.ieee.org
This paper presents a hybrid CT/DT0-2 multi-stage noise-shaping (MASH) delta-sigma
modulator (DSM) with a passive noise-shaping successive approximation register (NSSAR) …

Recent Advances in High-Resolution Hybrid Discrete-Time Noise-Shaping ADCs

D Jiang, SW Sin, L Qi, G Wang… - IEEE Open Journal of …, 2021 - ieeexplore.ieee.org
High precision data acquisition requires very-high-resolution Analog-to-digital converters
(ADC) for kHz speed or to keep a relatively high resolution for wider bandwidth (BW) around …

A 3.07 mW 30 MHz-BW 73.2 dB-SNDR Time-Interleaved Noise-Shaping SAR ADC With Self-Coupling Second-Order Error-Feedforward

S Zhao, M Guo, L Qi, D Xu, G Wang… - IEEE Journal of Solid …, 2023 - ieeexplore.ieee.org
A noise-shaping successive approximation register (NS-SAR) ADC combines the merits of
the-and SAR ADC, transforming it into an emerging ADC architecture to reach high …

An 8-MS/s 16-bit SAR ADC With Symmetric Complementary Switching and Split Passive Reference Segmentation in 180-nm Process

S Huang, Q Huang, Y Fan, Q Zhao… - … on Circuits and …, 2024 - ieeexplore.ieee.org
This paper presents an efficient 8-MS/s 16-bit successive approximation register (SAR)
analog-to-digital converter (ADC) with the proposed symmetric complementary switching …

A 24-OSR to Simplify Anti-Aliasing Filter 2MHz-BW 83dB-DR 3rd-order DT-DSM using FIA-Based Integrator and Noise-Shaping SAR Combined Digital Noise …

M Fukazawa, T Matsui - … on VLSI Technology and Circuits (VLSI …, 2023 - ieeexplore.ieee.org
This paper proposes a dynamic circuits-based discrete-time (DT) delta-sigma modulator
(DSM) with 2MHz bandwidth (BW) at an oversampling ratio (OSR) of 24 to simplify anti-alias …

Design and Implementation of a 16-bit Multi-mode 4-Channel Time-Interleaved Delta-Sigma Modulator with SNDR> 106 dB and DCE Compensation Based on FPGA

A Roshanpanah, P Torkzadeh, K Hajsadeghi… - Circuits, Systems, and …, 2024 - Springer
In this research, a second-order delta-sigma modulator (DSM) with 16-bit resolution is
implemented in VHDL and based on FPGA with a time-interleaved (TI) structure. The …

A Two-Channel Time-Interleaved Continuous-Time Third-Order CIFF-Based Delta-Sigma Modulator

Y Hu, Y Liu, X Qin, Y Liu, M Guo, SW Sin… - … on Circuits and …, 2023 - ieeexplore.ieee.org
This work introduces a two-channel time-interleaved (TI) continuous-time (CT) 3rd-order
delta-sigma modulator (DSM). It uses the information from one complete channel to predict …