AutoCC: Automatic Discovery of Covert Channels in Time-Shared Hardware
Covert channels enable information leakage between security domains that should be
isolated by observing execution differences in shared hardware. These channels can …
isolated by observing execution differences in shared hardware. These channels can …
Cut and forward: Safe and secure communication for FPGA system on chips
F Restuccia, R Kastner - IEEE Transactions on Computer-Aided …, 2022 - ieeexplore.ieee.org
Modern FPGA system on chips uses complex multimanager, multisubordinate on-chip
communication networks. Processor cores, hardware accelerators, DMA engines, and other …
communication networks. Processor cores, hardware accelerators, DMA engines, and other …
OPEN-CFR: Open-source Co-design Framework for Redundancy with DPR in COTS FPGA SoCs
Commercial-off-the-shelf (COTS) Field Programmable Gate Array (FPGA) systems-on-chip
(SoCs) are flexible platforms combining a Processing System (PS) featuring high …
(SoCs) are flexible platforms combining a Processing System (PS) featuring high …
SEIF: Augmented Symbolic Execution for Information Flow in Hardware Designs
K Ryan, M Gregoire, C Sturton - … of the 12th International Workshop on …, 2023 - dl.acm.org
We present SEIF, an exploratory methodology for information flow verification based on
symbolic execution. SEIF begins with a statically built overapproximation of the information …
symbolic execution. SEIF begins with a statically built overapproximation of the information …
SEIF: Augmented Symbolic Execution for Information Flow Verification
K Ryan, M Gregoire, C Sturton - … Support for Security and Privacy (HASP …, 2023 - dl.acm.org
We present SEIF, an exploratory methodology for information flow verification based on
symbolic execution. SEIF begins with a statically built overapproximation of the information …
symbolic execution. SEIF begins with a statically built overapproximation of the information …
SEIF: Augmented Symbolic Execution for Information Flow
K Ryan, M Gregoire, C Sturton - 2023 - par.nsf.gov
We present SEIF, an exploratory methodology for information flow verification based on
symbolic execution. SEIF begins with a statically built overapproximation of the information …
symbolic execution. SEIF begins with a statically built overapproximation of the information …
Towards Zero-Trust Hardware Architectures in Safety and Security Critical System-on-Chips
F Restuccia, R Kastner - 2024 IEEE 3rd Real-Time and …, 2024 - ieeexplore.ieee.org
Edge computing applications have strict requirements for latency, throughput, and energy.
Increasingly, there are more safety and security requirements due to system-level threats …
Increasingly, there are more safety and security requirements due to system-level threats …
[PDF][PDF] eXpect: On the Security Implications of Violations in AXI Implementations
M Zonta-Roudes, A Meza, N Hinderling… - 2024 - melisandezonta.com
The Arm Advanced eXtensible Interface (AXI) protocol is a specification for system-on-chip
(SoC) communication [14]. It consists of interfaces such as AXI-Lite and AXI-Full and is a part …
(SoC) communication [14]. It consists of interfaces such as AXI-Lite and AXI-Full and is a part …