Network-attached FPGAs for data center applications
FPGAs (Field Programmable Gate Arrays) are making their way into data centers (DC). They
are used as accelerators to boost the compute power of individual server nodes and to …
are used as accelerators to boost the compute power of individual server nodes and to …
An FPGA platform for hyperscalers
FPGAs (Field Programmable Gate Arrays) are making their way into data centers (DC). They
are used as accelerators to boost the compute power of individual server nodes and to …
are used as accelerators to boost the compute power of individual server nodes and to …
Analyzing the energy-efficiency of sparse matrix multiplication on heterogeneous systems: A comparative study of GPU, Xeon Phi and FPGA
Hardware accelerators have evolved as the most prominent vehicle to meet the demanding
performance and energy-efficiency constraints of modern computer systems. The prevalent …
performance and energy-efficiency constraints of modern computer systems. The prevalent …
Disaggregated FPGAs: Network performance comparison against bare-metal servers, virtual machines and linux containers
FPGAs (Field Programmable Gate Arrays) are making their way into data centers (DC). They
are used as accelerators to boost the compute power of individual server nodes and to …
are used as accelerators to boost the compute power of individual server nodes and to …
Sparse matrix multiplication using a single field programmable gate array module
According to some embodiments, a computer-implemented method for performing sparse
matrix dense matrix (SpMM) multiplication on a single field programmable gate array (FPGA) …
matrix dense matrix (SpMM) multiplication on a single field programmable gate array (FPGA) …
Accelerating arithmetic kernels with coherent attached FPGA coprocessors
The energy efficiency of computer systems can be increased by migrating computational
kernels that are known to under-utilize the CPU to an FPGA based coprocessor. In contrast …
kernels that are known to under-utilize the CPU to an FPGA based coprocessor. In contrast …
[HTML][HTML] Optimizing the Performance of the Sparse Matrix–Vector Multiplication Kernel in FPGA Guided by the Roofline Model
The widespread adoption of massively parallel processors over the past decade has
fundamentally transformed the landscape of high-performance computing hardware. This …
fundamentally transformed the landscape of high-performance computing hardware. This …
Sparse matrix multiplication using a single field programmable gate array module
According to some embodiments, a computer-implemented method for performing sparse
matrix dense matrix (SpMM) multiplication on a single field programmable gate array (FPGA) …
matrix dense matrix (SpMM) multiplication on a single field programmable gate array (FPGA) …
Exploring functional acceleration of OpenCL on FPGAs and GPUs through platform-independent optimizations
OpenCL has been proposed as a means of accelerating functional computation using FPGA
and GPU accelerators. Although it provides ease of programmability and code portability …
and GPU accelerators. Although it provides ease of programmability and code portability …
Freac cache: Folded-logic reconfigurable computing in the last level cache
The need for higher energy efficiency has resulted in the proliferation of accelerators across
platforms, with custom and reconfigurable accelerators adopted in both edge devices and …
platforms, with custom and reconfigurable accelerators adopted in both edge devices and …