System, method, and computer program product for improving memory systems

MS Smith - US Patent 9,432,298, 2016 - Google Patents
H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid
state devices; Multistep manufacturing processes thereof the devices being of types …

Error characterization, mitigation, and recovery in flash-memory-based solid-state drives

Y Cai, S Ghose, EF Haratsch, Y Luo… - Proceedings of the …, 2017 - ieeexplore.ieee.org
NAND flash memory is ubiquitous in everyday life today because its capacity has
continuously increased and cost has continuously decreased over decades. This positive …

Overcoming the challenges of crossbar resistive memory architectures

C Xu, D Niu, N Muralimanohar… - 2015 IEEE 21st …, 2015 - ieeexplore.ieee.org
The scalability of DRAM faces challenges from increasing power consumption and the
difficulty of building high aspect ratio capacitors. Consequently, emerging memory …

RAIDR: Retention-aware intelligent DRAM refresh

J Liu, B Jaiyen, R Veras, O Mutlu - ACM SIGARCH Computer …, 2012 - dl.acm.org
Dynamic random-access memory (DRAM) is the building block of modern main memory
systems. DRAM cells must be periodically refreshed to prevent loss of data. These refresh …

AVATAR: A variable-retention-time (VRT) aware refresh for DRAM systems

MK Qureshi, DH Kim, S Khan, PJ Nair… - 2015 45th Annual …, 2015 - ieeexplore.ieee.org
Multirate refresh techniques exploit the non-uniformity in retention times of DRAM cells to
reduce the DRAM refresh overheads. Such techniques rely on accurate profiling of retention …

A survey of architectural techniques for DRAM power management

S Mittal - … Journal of High Performance Systems Architecture, 2012 - inderscienceonline.com
Recent trends of CMOS technology scaling and wide-spread use of multicore processors
have dramatically increased the power consumption of main memory. It has been estimated …

Improving DRAM performance by parallelizing refreshes with accesses

KKW Chang, D Lee, Z Chishti… - 2014 IEEE 20th …, 2014 - ieeexplore.ieee.org
Modern DRAM cells are periodically refreshed to prevent data loss due to leakage.
Commodity DDR (double data rate) DRAM refreshes cells at the rank level. This degrades …

HiRA: Hidden row activation for reducing refresh latency of off-the-shelf DRAM chips

AG Yağlikçi, A Olgun, M Patel, H Luo… - 2022 55th IEEE/ACM …, 2022 - ieeexplore.ieee.org
DRAM is the building block of modern main memory systems. DRAM cells must be
periodically refreshed to prevent data loss. Refresh operations degrade system performance …

The reach profiler (reaper) enabling the mitigation of dram retention failures via profiling at aggressive conditions

M Patel, JS Kim, O Mutlu - ACM SIGARCH Computer Architecture News, 2017 - dl.acm.org
Modern DRAM-based systems suffer from significant energy and latency penalties due to
conservative DRAM refresh standards. Volatile DRAM cells can retain information across a …

ArchShield: Architectural framework for assisting DRAM scaling by tolerating high error rates

PJ Nair, DH Kim, MK Qureshi - ACM SIGARCH Computer Architecture …, 2013 - dl.acm.org
DRAM scaling has been the prime driver for increasing the capacity of main memory system
over the past three decades. Unfortunately, scaling DRAM to smaller technology nodes has …