Measurement based wcet analysis for multi-core architectures

H Shah, A Coombes, A Raabe, K Huang… - Proceedings of the 22Nd …, 2014 - dl.acm.org
The interference on shared resources caused by concurrently executing applications
unpredictably prolongs their execution. Hence, determination of the Worst Case Execution …

A performance conserving approach for reducing memory power consumption in multi-core systems

J Fang, J Lu, M Wang, H Zhao - Journal of Circuits, Systems and …, 2019 - World Scientific
With more cores integrated into a single chip and the fast growth of main memory capacity,
the DRAM memory design faces ever increasing challenges. Previous studies have shown …

Multi-input Asynchronous Arbiter with Parallel Connection of Input Signals. Arbitration in Conditions of Superscalarity

D Tyanev, Y Petkova - … of the 22nd International Conference on …, 2021 - dl.acm.org
The research is devoted to problems caused by the impossibility to satisfy the requests for
immediate service of a subscriber of a given resource in the conditions of various forms of …

Predictable and high performance multi-core architectures

H Shah - 2015 - mediatum.ub.tum.de
Multi-core architectures could provide the computational power needed to the demanding
hard real-time systems. However, the interference on the shared resources makes the Worst …

[PDF][PDF] Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties

S Kaiser, S Mazzini, P Azzoni - 2016 - cordis.europa.eu
This document summarizes all standardization activities that were undertaken by CONTREX
project partners along the project execution. This includes standards proposals planned or …