Cognitive operations based on empirically constructed knowledge graphs
Mechanisms are provided for performing a cognitive operation. The mechanisms receive an
original graph data structure comprising nodes and edges between nodes and activity log …
original graph data structure comprising nodes and edges between nodes and activity log …
Timing violation debugging inside place and route tool
M Dinter, J Dirks, HJ Preuthen - US Patent 7,747,975, 2010 - Google Patents
(63) Continuation of application No. 91S, Illed on ing cells in the circuit design, the specific
cell having a timing Aug. 31, 2005, now Pat. No. 7,325,215. characteristic,(B) generating a …
cell having a timing Aug. 31, 2005, now Pat. No. 7,325,215. characteristic,(B) generating a …
Apparatus for a routing system
JC Lien, M Zhao - US Patent App. 11/590,765, 2007 - Google Patents
The invention details methods and apparatus for a routing system or router that includes a
model. The model can be in many different forms including but not limited to: resolution …
model. The model can be in many different forms including but not limited to: resolution …
Method for application of network flow techniques under constraints
JH Anderson, SK Nag, G Stenz… - US Patent …, 2006 - Google Patents
1/2003 Cho et al....................... T16. 8 252 accepts a flow network may lead to infeasible
solutions. The infeasible solutions can be removed by an iterative process of changing the …
solutions. The infeasible solutions can be removed by an iterative process of changing the …
Method and apparatus for placing circuit modules
S Teig, JL Ganley - US Patent 7,055,120, 2006 - Google Patents
23 Design Automation Conference, 1986, pp. 708–714. Fang, S. et al., Constrained Via
Minimization with Practical Considerations for Multi-Layer VLSI/PCB Routing Prob lems, 28." …
Minimization with Practical Considerations for Multi-Layer VLSI/PCB Routing Prob lems, 28." …
Timing and signal integrity analysis of integrated circuits with semiconductor process variations
V Kariat, JR Phillips, I Keller - US Patent 7,882,471, 2011 - Google Patents
BACKGROUND Designing and manufacturing semiconductor integrated circuits is a
challenge. Variations in semiconductor process ing of an integrated circuit can cause …
challenge. Variations in semiconductor process ing of an integrated circuit can cause …
Architectural physical synthesis
KS McElvain, B Lemonnier, W Halpin - US Patent 8,819,608, 2014 - Google Patents
CN 1687934. A 10/2005 CN 1851717 A 10, 2006 JP O5-342290 A 12/1993 JP 06-266801 A
9, 1994 JP 08-202758 A 8, 1996 JP 10-171857 A 6, 1998 JP 11-085819 A 3, 1999 JP O1 …
9, 1994 JP 08-202758 A 8, 1996 JP 10-171857 A 6, 1998 JP 11-085819 A 3, 1999 JP O1 …
Method and apparatus for computing placement costs
S Teig, JL Ganley - US Patent 7,080,336, 2006 - Google Patents
US7080336B2 - Method and apparatus for computing placement costs - Google Patents
US7080336B2 - Method and apparatus for computing placement costs - Google Patents Method …
US7080336B2 - Method and apparatus for computing placement costs - Google Patents Method …
Timing budgeting of nested partitions for hierarchical integrated circuit designs
S Arora, O Levitsky, A Kumar, S Singh - US Patent 8,977,995, 2015 - Google Patents
In one embodiment, a method of designing an integrated circuit is disclosed, including
receiving a plurality oftop level timing constraints and a description of the integrated circuit …
receiving a plurality oftop level timing constraints and a description of the integrated circuit …
Routing method and apparatus
S Teig, O Buset, E Jacques - US Patent 6,931,616, 2005 - Google Patents
A routing method that uses diagonal routes. This method routes several nets within a region
of a circuit layout. Each net includes a set of pins in the region. The method initially partitions …
of a circuit layout. Each net includes a set of pins in the region. The method initially partitions …