Multilevel semiconductor device and structure with memory
Z Or-Bach, JW Han - US Patent 10,515,981, 2019 - Google Patents
US10515981B2 - Multilevel semiconductor device and structure with memory - Google
Patents US10515981B2 - Multilevel semiconductor device and structure with memory …
Patents US10515981B2 - Multilevel semiconductor device and structure with memory …
Integrated circuit device and structure
Z Or-Bach, DC Sekar, B Cronquist - US Patent 9,099,526, 2015 - Google Patents
US9099526B2 - Integrated circuit device and structure - Google Patents US9099526B2 -
Integrated circuit device and structure - Google Patents Integrated circuit device and structure …
Integrated circuit device and structure - Google Patents Integrated circuit device and structure …
3D semiconductor device and structure
Z Or-Bach, B Cronquist - US Patent 10,840,239, 2020 - Google Patents
H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state
components formed in or on a common substrate including semiconductor components …
components formed in or on a common substrate including semiconductor components …
Semiconductor memory device and structure
Z Or-Bach, JW Han - US Patent 11,956,952, 2024 - Google Patents
A device, including: a first structure including first memory cells, the first memory cells
including first transistors; and a second structure including second memory cells, the second …
including first transistors; and a second structure including second memory cells, the second …
Methods for processing a 3D semiconductor device
Z Or-Bach, B Cronquist - US Patent 10,297,586, 2019 - Google Patents
A method for processing a 3D semiconductor device, the method including: providing a
wafer including a plurality of first dies, the plurality of first dies including a first transistor layer …
wafer including a plurality of first dies, the plurality of first dies including a first transistor layer …
Semiconductor and optoelectronic devices
Z Or-Bach, D Sekar - US Patent 9,419,031, 2016 - Google Patents
H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state
components formed in or on a common substrate including semiconductor components …
components formed in or on a common substrate including semiconductor components …
Multi-level semiconductor memory device and structure
Z Or-Bach, JW Han - US Patent 10,418,369, 2019 - Google Patents
A multilevel semiconductor device including: a first level including a first array of first memory
cells and first control line; a second level including a second array of second memory cells …
cells and first control line; a second level including a second array of second memory cells …
Semiconductor device and structure
Z Or-Bach, B Cronquist - US Patent 10,224,279, 2019 - Google Patents
H01L23/522—Arrangements for conducting electric current within the device in operation
from one component to another, ie interconnections, eg wires, lead frames including …
from one component to another, ie interconnections, eg wires, lead frames including …
3D semiconductor device, fabrication method and system
Z Or-Bach, DC Sekar, B Cronquist… - US Patent 10,217,667, 2019 - Google Patents
A 3D memory device, the device including: a first single crystal layer including memory
peripheral circuits; a first memory layer including a first junction-less transistor; a second …
peripheral circuits; a first memory layer including a first junction-less transistor; a second …
Semiconductor device and structure
Z Or-Bach, B Cronquist - US Patent 9,117,749, 2015 - Google Patents
H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state
components formed in or on a common substrate including semiconductor components …
components formed in or on a common substrate including semiconductor components …