Steps toward automated deprocessing of integrated circuits

EL Principe, N Asadizanjani, D Forte… - … for Testing and …, 2017 - dl.asminternational.org
This paper discusses the development of an extensible programmatic workflow that
leverages evolving technologies in 2D/3D imaging, distributed instrument control, image …

Nondestructive sample imaging

EM Lavely, AJ Marcinuk, AV Masurkar… - US Patent …, 2019 - Google Patents
A system and method for imaging a sample having a complex structure (such as an
integrated circuit) implements two modes of operation utilizing a common electron beam …

[PDF][PDF] Fast, full chip image stitching of nanoscale integrated circuits

D Zhang, G Van Der Wal, P Miller, D Stoker… - Technical …, 2019 - academia.edu
The rapid progression of semiconductor technology has significantly impacted the ability to
examine and analyze complex integrated circuits (ICs). Small device feature sizes …

Sample manipulation for nondestructive sample imaging

CL Willis, EM Lavely, AJ Marcinuk, PR Moffitt… - US Patent …, 2020 - Google Patents
(57) ABSTRACT A system and method for imaging a sample having a complex structure
(such as an integrated circuit). The sample is placed on a motion system that moves the …

Thermal Exposure Effects of Backside Thinned Flip-Chip Device on Visible Light Probing

J Li, E Halteh, J Elliott, HL Marks… - … for Testing and …, 2018 - dl.asminternational.org
We report the results of our studies on thermally induced surface topography changes in
ultra-thinned silicon flip-chip packaged devices. Previous results showed that over polishing …

Targeted Silicon Ultra-thinning by Contour Milling for Advanced Fault Isolation

WS Teo, MS Wei, V Narang, CL Gan… - … for testing and …, 2019 - dl.asminternational.org
In this paper, we present methods for targeted silicon thinning by contour milling to
overcome challenges associated with thinning large devices to under 5 µm remaining …

Submicron thinning of finFET devices with high power density observed in 10/7nm process nodes using high aspect ratio trenches

N Bakken, V Vlasyuk, M Beal… - … for Testing and …, 2019 - dl.asminternational.org
Infrared optical probing techniques that have significant applications to and continued
development for silicon physical debug have existed for decades. More recently, resolution …

Backside Preparation and Optics

J Colvin, C Colvin - Microelectronics Failure Analysis: Desk …, 2019 - books.google.com
This tutorial will assist the analyst in making decisions on backside thinning and polishing
requirements and hopefully dispel many of the associated myths and assumptions. Many …

Electrical Invasiveness of Grinding and Polishing Silicon Integrated Circuits Down to 1 μm Remaining Silicon Thickness

R Chivas, S Silverman, M DiBattista… - … for Testing and …, 2016 - dl.asminternational.org
Anticipating the end of life for IR-based failure analysis techniques, a method of global
backside preparation to ultra-thin remaining silicon thickness (RST) has been developed …

Nanofabricated structures for sub-beam resolution and spectral enhancement in tomographic imaging

EM Lavely, AV Masurkar, TJ Stark - US Patent 11,340,179, 2022 - Google Patents
Techniques are provided for tomographic imaging with sub-beam resolution and spectral
enhancement. A system implementing the techniques according to an embodiment includes …