(57) ABSTRACT A single die driver integrated circuit is coupled to an input portion having a
single inductor receiving a low voltage source and configured to drive a capacitive load with …

Disclosed is a successive-approximation register (SAR) analog-to-digital converter (ADC).
The SAR ADC may include a capacitor-resistor hybrid digital-to-analog converter (DAC) …

(57) ABSTRACT A single ended n-bit hybrid digital-to-analog converter is configured to
receive as an input an analog signal and produce an n-bit digital output. The converter …

(57) ABSTRACT A driver for a circuit with a capacitive load is configured for coupling to a
voltage source which provides a DC input voltage, and is configured to generate an output …

Analog-digital converter configured for conversion of an input voltage, represented by a pair
of input potentials, into a binary code using successive approximation. The analog-digital …

A single-ended successive approximation register (SAR) analog-to-digital converter (ADC)
includes a first digital-to-analog converter (DAC) having a first capacitor associated with a …

To reduce the overall reference charge needed to perform operations, analog-to-digital
converters can maintain reference voltage connections of the bit trial capacitors of the digital …

A successive approximation analog-to-digital converter (SAR ADC) and an operation
method thereof are provided. The SAR ADC, which alternately operates in a sampling phase …

(57) ABSTRACT A successive approximation register analog to digital con verter (SAR ADC)
is provided in which impact of dielectric absorption is reduced with a correction circuit …

The present disclosure relates to a high-speed and low-power successive approximation
register analog-to-digital converter (SAR ADC) and an analog-to-digital conversion method …