Design insights of nanosheet FET and CMOS circuit applications at 5-nm technology node

VB Sreenivasulu, V Narendar - IEEE Transactions on Electron …, 2022 - ieeexplore.ieee.org
In this article, FinFET, vertically stacked gate-all-around (GAA) nanowire (NW), and
nanosheet (NS) FETs performance are estimated with equal effective channel widths () at …

Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes

VB Sreenivasulu, V Narendar - Microelectronics Journal, 2021 - Elsevier
In this paper, for the first time, we have investigated the DC, analog/RF, and linearity metrics
of asymmetric spacer junctionless (JL) Gate-All-Around (GAA) vertically stacked nanowire …

Demonstration of a nanosheet FET with high thermal conductivity material as buried oxide: Mitigation of self-heating effect

S Rathore, RK Jaisawal, PN Kondekar… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
Self-heating-induced thermal degradation is a severe issue in nonplanar MOS architectures.
Especially in stacked gate-all-around (GAA) nanosheet FET (NSFET), the self-heating effect …

Fast and expandable ANN-based compact model and parameter extraction for emerging transistors

H Jeong, S Woo, J Choi, H Cho, Y Kim… - IEEE Journal of the …, 2023 - ieeexplore.ieee.org
In this paper, we present a fast and expandable artificial neural network (ANN)-based
compact model and parameter extraction flow to replace the existing complicated compact …

A vertically stacked nanosheet gate-all-around FET for biosensing application

C Li, F Liu, R Han, Y Zhuang - IEEE Access, 2021 - ieeexplore.ieee.org
In this paper, a vertically stacked nanosheet gate-all-around field-effect transistor (GAA-
NSFET) as a label-free biosensor has been proposed and investigated. The influences of …

Machine-learning-based compact modeling for sub-3-nm-node emerging transistors

SM Woo, HJ Jeong, JY Choi, HM Cho, JT Kong… - Electronics, 2022 - mdpi.com
In this paper, we present an artificial neural network (ANN)-based compact model to
evaluate the characteristics of a nanosheet field-effect transistor (NSFET), which has been …

[PDF][PDF] Review of nanosheet transistors technology

FNAH Agha, YH Naif, MN Shakib - Tikrit Journal of Engineering Sciences, 2021 - iasj.net
Nano-sheet transistor can be defined as a stacked horizontally gate surrounding the
channel on all direction. This new structure is earning extremely attention from research to …

Performance evaluation of spacer dielectric engineered vertically stacked junctionless nanosheet FET for sub-5 nm technology node

S Valasa, S Tayal, LR Thoutam - ECS Journal of Solid State …, 2022 - iopscience.iop.org
This manuscript for the first time provides insights on the impact of different spacer materials
for the vertically stacked Junctionless Nanosheet Field Effect Transistor (JL-NSFET). The …

Design and performance assessment of graded channel gate-all-around silicon nanowire FET for biosensing applications

Ashima, V Dhandapani, B Raj - Silicon, 2023 - Springer
In this paper, we present a graded channel gate-all-around silicon nanowire-FET biosensor
working on dielectric modulation through a cavity carved at the center of the gate for label …

Recent progress on field-effect transistor-based biosensors: device perspective

B Smaani, F Nafa, MS Benlatrech… - Beilstein Journal of …, 2024 - beilstein-journals.org
Over the last few decades, field-effect transistor (FET)-based biosensors have demonstrated
great potential across various industries, including medical, food, agriculture, environmental …