TERAFLUX: Harnessing dataflow in next generation teradevices

R Giorgi, RM Badia, F Bodin, A Cohen… - Microprocessors and …, 2014 - Elsevier
The improvements in semiconductor technologies are gradually enabling extreme-scale
systems such as teradevices (ie, chips composed by 1000 billion of transistors), most likely …

The TERAFLUX project: Exploiting the dataflow paradigm in next generation teradevices

M Solinas, RM Badia, F Bodin, A Cohen… - … on Digital System …, 2013 - ieeexplore.ieee.org
Thanks to the improvements in semiconductor technologies, extreme-scale systems such as
teradevices (ie, composed by 1000 billion of transistors) will enable systems with 1000+ …

[PDF][PDF] Simulating the future kilo-x86-64 core processors and their infrastructure

A Portero, A Scionti, Z Yu, P Faraboschi… - Proceedings of the …, 2012 - academia.edu
The continuous improvements offered by the silicon technology enables the integration of
always increasing number of cores on a single chip. Following this trend, it is expected to …

A design space exploration tool set for future 1k-core high-performance computers

R Giorgi, M Procaccini, F Khalili - Proceedings of the Rapid Simulation …, 2019 - dl.acm.org
Given the constantly growing complexity of multi-core architectures, Design Space
Exploration (DSE) tools play an important role to evaluate different design options. In this …

PSCR: a coherence protocol for eliminating passive sharing in shared-bus shared-memory multiprocessors

R Giorgi, CA Prete - IEEE Transactions on Parallel and …, 1999 - ieeexplore.ieee.org
In high-performance general-purpose workstations and servers, the workload can be
typically constituted of both sequential and parallel applications. Shared-bus shared …

Exploring future many-core architectures: The TERAFLUX evaluation framework

R Giorgi - Advances in Computers, 2017 - Elsevier
The design of new computer systems always requires a strong simulation effort in order to
evaluate different design options. This is especially true if the system is to be produced at a …

[PDF][PDF] Some considerations about passive sharing in shared-memory multiprocessors

CA Prete, G Prina, R Giorgi, L Ricciardi - IEEE TCCA Newsletter, 1997 - researchgate.net
In a multiprocessor system, process migration guarantees load balance between processors
but causes passive sharing, since private data blocks of a process can become resident in …

Simulation study of memory performance of SMP multiprocessors running a TPC-W workload

P Foglia, R Giorgi, CA Prete - IEE Proceedings-Computers and Digital …, 2004 - IET
The infrastructure to support electronic commerce is one of the areas where more
processing power is needed. A multiprocessor system can offer advantages for running …

Fine-grain design space exploration for a cartographic SoC multiprocessor

A Bechini, P Foglia, CA Prete - ACM SigArch Computer Architecture …, 2003 - dl.acm.org
Traditionally, in the field of embedded systems low power consumption and low cost have
been always regarded as stringent specification constraints. In recent years, high …

Performance‐steered design of software architectures for embedded multicore systems

A Bechini, CA Prete - Software: Practice and Experience, 2002 - Wiley Online Library
Many software applications demanding a considerable computing power are moving
towards the field of embedded systems (and, in particular, hand‐held devices). A possible …