In the sub-100-nm CMOS generation, a large local Vth variability degrades the 6T-SRAM
cell stability, so that we have to consider this local variability as well as the global variability …

A voltage scalable 0.26 V, 64 kb 8T SRAM with 512 cells per bitline is implemented in a 130
nm CMOS process. Utilization of the reverse short channel effect in a SRAM cell design …

In this paper, we present a new 9T SRAM cell that has good write ability and improves read
stability at the same time. Simulation results show that the proposed design increases read …

Embodiments include an array of SRAM cells, an SRAM cell, and methods of forming the
same. An embodiment is an array of static random access memory (SRAM) cells includ ing a …

Low-power SRAM design is crucial since it takes a large fraction of total power and die area
in high-performance processors. Reducing voltage swing of the bit-line is an effective way to …

Subthreshold and near-threshold operations are viable approaches towards reducing both
static and dynamic power in Static Random Access Memory (SRAM). However, supply …

In order to meet the ultra-low power requirement of modern digital systems, voltage scaling
is a fruitful technique that is widely adopted. However, the voltage scaling at ultra-scaled …

Read and write assist techniques are now commonly used to lower the minimum operating
voltage (V min) of an SRAM. In this paper, we review the efficacy of four leading write-assist …

We propose a wafer level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly
reliable Cu E-trim fuse repair for an embedded 6T-SRAM to achieve a known good die …

We propose an access scheme for a synchronous dual-port (DP) SRAM that minimizes the
8T-DP-cell area and maintains cell stability. A priority row decoder circuit and shifted bit-line …