The apparent saturation of aggressive Moore's law scaling of semiconductor technologies is
pushing the boundaries of traditional packaging and integration schemes to accommodate …

This paper describes the design of a 10 GHz phase-locked loop (PLL) for a 40 Gb/s serial
link transmitter (TX). A two-stage ring oscillator is used to provide a four-phase, 10 GHz clock …

In this paper, we describe the performance and power benefits of our Fine Pitch integration
scheme on a Silicon Interconnect Fabric (Si IF). Here we propose a Simple Universal …

Pre-charging two or more sets of nodes to set a differential output of a multi-input summation
latch connected to the two or more sets of nodes in a pre-charged state, the two or more sets …

Pushed by the ever-increasing demand of internet traffic, high-speed serial interfaces are
expected to reach 400-Gb/s aggregate data rates in near future. At receiver (RX) side, phase …

The Silicon-Interconnect Fabric (Si-IF) is a highly scalable platform for heterogenous
integration of dielets using a fine interconnect pitch (? 10 µm) and small inter-dielet spacing …

This paper presents a 40-Gb/s transmitter (TX) and receiver (RX) chipset for chip-to-chip
communications in a 65-nm CMOS process. The TX implements a quarter-rate multi …

This article presents a 50–112-Gb/s current-mode four-level pulse amplitude modulation
(PAM-4) transmitter with a two-tap fractional-spaced feed-forward equalizer (FFE). The …

This paper discusses a 56-Gb/s PAM4 receiver analog-front end (AFE) implemented in
TSMC 40-nm CMOS process. The system consists of a differential 100-Ω termination, a two …

We present a high-accuracy, low-jitter, multi-phase clock generator (MPCG) based on a
multi-phase, injection-locked ring oscillator (MPIL-ROSC) with a quadrature delay-locked …