A computer-implemented method of performing physical synthesis in a chip design process
using hierarchical wire-pin co-optimization, a system, and a computer program product are …

A system and a computer implemented method for interior pinning in a macro block of an
integrated circuit are provided. The method includes receiving child level information of the …

A system to develop an integrated circuit includes a latch identifier module to identify a first
child latch placed at a first location in a first child macro of a parent macro and a second …

Circuit pin constraints input to a design tool specify respective sets of circuit pins belonging
to circuit blocks, and input interface pin constraints specify respective sets of interface pins …

There has been increasing interest in the design of array processors for the last several
years. The array processors require adders and subtractors as the hardware instead of …

Based on a directive in a control file, a processor pre-routes, within a hierarchical integrated
circuit design, a signal through one or more levels of design hierarchy between a signal …

A specification for a modular circuit design includes a mapping from global clock domains to
global voltage domains. A processor assigns, to a first instance of a clocked primitive …

A system and method to perform physical synthesis to transition a logic design to a physical
layout of an integrated circuit include obtaining an initial netlist that indicates all components …