A survey of architectural techniques for improving cache power efficiency
S Mittal - Sustainable Computing: Informatics and Systems, 2014 - Elsevier
Modern processors are using increasingly larger sized on-chip caches. Also, with each
CMOS technology generation, there has been a significant increase in their leakage energy …
CMOS technology generation, there has been a significant increase in their leakage energy …
Drowsy caches: simple techniques for reducing leakage power
On-chip caches represent a sizable fraction of the total power consumption of
microprocessors. Although large caches can significantly improve performance, they have …
microprocessors. Although large caches can significantly improve performance, they have …
Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM
Large last-level caches (L 3 Cs) are frequently used to bridge the performance and power
gap between processor and memory. Although traditional processors implement caches as …
gap between processor and memory. Although traditional processors implement caches as …
[图书][B] Industrial communication technology handbook
R Zurawski - 2014 - books.google.com
Featuring contributions from major technology vendors, industry consortia, and government
and private research establishments, the Industrial Communication Technology Handbook …
and private research establishments, the Industrial Communication Technology Handbook …
Managing multi-configuration hardware via dynamic working set analysis
AS Dhodapkar, JE Smith - ACM SIGARCH Computer Architecture News, 2002 - dl.acm.org
Microprocessors are designed to provide good average performance over a variety of
workloads. This can lead to inefficiencies both in power and performance for individual …
workloads. This can lead to inefficiencies both in power and performance for individual …
[图书][B] Computer architecture techniques for power-efficiency
S Kaxiras, M Martonosi - 2008 - books.google.com
In the last few years, power dissipation has become an important design constraint, on par
with performance, in the design of new computer systems. Whereas in the past, the primary …
with performance, in the design of new computer systems. Whereas in the past, the primary …
A highly configurable cache architecture for embedded systems
Energy consumption is a major concern in many embedded computing systems. Several
studies have shown that cache memories account for about 50% of the total energy …
studies have shown that cache memories account for about 50% of the total energy …
Counter-based cache replacement and bypassing algorithms
M Kharbutli, Y Solihin - IEEE Transactions on Computers, 2008 - ieeexplore.ieee.org
Recent studies have shown that, in highly associative caches, the performance gap between
the least recently used (LRU) and the theoretical optimal replacement algorithms is large …
the least recently used (LRU) and the theoretical optimal replacement algorithms is large …
[PDF][PDF] Hotleakage: A temperature-aware model of subthreshold and gate leakage for architects
Y Zhang, D Parikh, K Sankaranarayanan, K Skadron… - 2003 - cs.virginia.edu
This report introduces HotLeakage, an architectural model for subthreshold and gate
leakage that we have developed here at the University of Virginia. The most important …
leakage that we have developed here at the University of Virginia. The most important …