Low-power SAR ADC design: Overview and survey of state-of-the-art techniques
This paper presents an overview for low-power successive approximation register (SAR)
analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and …
analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and …
Energy-efficient cooperative spectrum sensing: A survey
The article analyzes the problem of energy efficient techniques in cooperative spectrum
sensing (CSS). Although it was proven that single-device sensing is not sufficient for reliable …
sensing (CSS). Although it was proven that single-device sensing is not sufficient for reliable …
A twin-8T SRAM computation-in-memory unit-macro for multibit CNN-based AI edge processors
Computation-in-memory (CIM) is a promising candidate to improve the energy efficiency of
multiply-and-accumulate (MAC) operations of artificial intelligence (AI) chips. This work …
multiply-and-accumulate (MAC) operations of artificial intelligence (AI) chips. This work …
A local computing cell and 6T SRAM-based computing-in-memory macro with 8-b MAC operation for edge AI chips
This article presents a computing-in-memory (CIM) structure aimed at improving the energy
efficiency of edge devices running multi-bit multiply-and-accumulate (MAC) operations. The …
efficiency of edge devices running multi-bit multiply-and-accumulate (MAC) operations. The …
A reconfigurable 12-to-18-Bit dynamic zoom ADC with Pole-optimized technique
Y Liang, J Ren, L Chen, H Lan, J Song… - … on Circuits and …, 2023 - ieeexplore.ieee.org
This paper presents a resolution-reconfigurable discrete-time dynamic zoom analog-to-
digital converter (ADC) with a 20-kHz bandwidth. It employs a coarse 6-bit successive …
digital converter (ADC) with a 20-kHz bandwidth. It employs a coarse 6-bit successive …
NeuralTree: A 256-channel 0.227-μJ/class versatile neural activity classification and closed-loop neuromodulation SoC
Closed-loop neural interfaces with on-chip machine learning can detect and suppress
disease symptoms in neurological disorders or restore lost functions in paralyzed patients …
disease symptoms in neurological disorders or restore lost functions in paralyzed patients …
An injectable 64 nW ECG mixed-signal SoC in 65 nm for arrhythmia monitoring
A syringe-implantable electrocardiography (ECG) monitoring system is proposed. The noise
optimization and circuit techniques in the analog front-end (AFE) enable 31 nA current …
optimization and circuit techniques in the analog front-end (AFE) enable 31 nA current …
A 1 GS/s 10b 18.9 mW time-interleaved SAR ADC with background timing skew calibration
S Lee, AP Chandrakasan… - IEEE Journal of Solid-State …, 2014 - ieeexplore.ieee.org
This paper presents a time-interleaved (TI) SAR ADC which enables background timing
skew calibration without a separate timing reference channel and enhances the conversion …
skew calibration without a separate timing reference channel and enhances the conversion …
A 15.2-ENOB 5-kHz BW 4.5- W Chopped CT -ADC for Artifact-Tolerant Neural Recording Front Ends
H Chandrakumar, D Marković - IEEE Journal of Solid-State …, 2018 - ieeexplore.ieee.org
Implantable closed-loop neural stimulation is desirable for clinical translation and basic
neuroscience research. Neural stimulation generates large artifacts at the recording sites …
neuroscience research. Neural stimulation generates large artifacts at the recording sites …
A 16-bit 16-MS/s SAR ADC with on-chip calibration in 55-nm CMOS
J Shen, A Shikata, LD Fernando… - IEEE Journal of Solid …, 2018 - ieeexplore.ieee.org
This paper presents a successive approximation register (SAR) analog-to-digital converter
(ADC) that is much smaller and faster than other recently reported precision (16-bit and …
(ADC) that is much smaller and faster than other recently reported precision (16-bit and …