Dynamic current sharing mechanism analysis of paralleled SiC MOSFETs considering parasitic mutual inductances based on an improved model
J Lv, C Chen, B Liu, Y Yan, Z Zheng… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
The dynamic current imbalance between paralleled SiC mosfet s can cause unbalanced
switching losses and limit the current capacity. It is essential to investigate the influences of …
switching losses and limit the current capacity. It is essential to investigate the influences of …
Layout-dominated dynamic current balancing analysis of multichip sic power modules based on coupled parasitic network model
Multichip silicon carbide (SiC) power modules with Kelvin-source connections are
commonly used in applications requiring large capacity. As a result of the parasitic effect …
commonly used in applications requiring large capacity. As a result of the parasitic effect …
Symmetric and Staggered Terminal Layouts for Enhanced Current Balance and Reduced Parasitic Inductance in SiC Power Modules
Y Wang, X Jiang, S Yuan, R Ouyang… - … on Power Electronics, 2024 - ieeexplore.ieee.org
This paper introduces a fully symmetric layout for a 4-parallel SiC MOSFET half-bridge
power module, wherein each power loop within the module exhibits physical and electrical …
power module, wherein each power loop within the module exhibits physical and electrical …
A Dynamic Current Sharing Model of Multichip Parallel SiC MOSFETs Considering Layout-Dominated Mutual Inductance Coupling
Z Zheng, C Chen, J Lv, Y Yan, J Liu… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
Dynamic current imbalance of parallel SiC MOSFETs can lead to uneven losses and even
thermal runaway. Unbalanced parasitic parameters dominated by layout are one of the main …
thermal runaway. Unbalanced parasitic parameters dominated by layout are one of the main …
A Quantitative Analytical Model of Paralleled SiC MOSFETs for Calculating Unbalanced Switching Currents and Energy
J Lv, C Chen, Y Yan, B Liu, Z Zheng… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
Uneven dynamic currents between paralleled silicon carbide (SiC) metal-oxide-
semiconductor field-effect transistors (mosfet s) can cause unbalanced switching losses …
semiconductor field-effect transistors (mosfet s) can cause unbalanced switching losses …
A Dynamic Current Balancing Method for Paralleled SiC MOSFETs with Gate-branch Full-coupled Inductors
J Lv, Y Yan, J Liu, B Liu, Z Zheng… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
In multichip SiC power modules, unbalanced dynamic currents between the paralleled dies
can induce unbalanced switching losses and junction temperatures, reducing the device's …
can induce unbalanced switching losses and junction temperatures, reducing the device's …
A High Performance GaN Power Module with Parallel Packaging for High Current and Low Voltage Traction Inverter Applications
Gallium nitride (GaN) power semiconductors are being explored as promising alternatives
for the next generation of high-power traction inverters, suitable for both high-and low …
for the next generation of high-power traction inverters, suitable for both high-and low …
A Negative-Feedback Gate-Loop for Current Balancing Paralleled SiC MOSFETs based on a Differential Mode Inductor
Z Cao, R Zhang, S Wang, E Peng - IEEE Access, 2024 - ieeexplore.ieee.org
Using paralleled SiC MOSFETs is an economical and commonly-used solution for high-
power applications. However, the dynamic unbalanced currents during TURN-ON and …
power applications. However, the dynamic unbalanced currents during TURN-ON and …
Influencing factors and suppressing methods of current imbalance for parallel-connected SiC MOSFETs: A review
J Qiao, B Zhao, P Sun, Y Cai… - 2022 IEEE 5th …, 2022 - ieeexplore.ieee.org
Silicon carbide MOSFETs are often applied in parallel connection because of low monolithic
current level. However, current imbalance caused by parallel connection challenges the …
current level. However, current imbalance caused by parallel connection challenges the …
Power Board Design for Parallel SiC MOSFET Characterization
MG Spitaleri, G Scarcella, G Scelba… - … Congress & Expo …, 2024 - ieeexplore.ieee.org
The primary objective of this paper is to present the design of a power board specifically
developed to investigate the impact of parameters and layout mismatches of paralleled SiC …
developed to investigate the impact of parameters and layout mismatches of paralleled SiC …