Introducing partial programmability in circuits by replacing some gates with look up tables
(LUTs) can be an effective way to improve post-silicon or in-field rectification and debugging …

In this paper, we present techniques for partial synthesis through sampling mostly for
combinational circuits. Here partial synthesis means that most parts of the target circuits are …

It is extremely difficult to provide 100% correctness of fabricated high performance circuits.
Manufactured circuits may have logical and electrical bugs, Trojan Circuits (TCs) inclusions …

A combinational circuit C is considered. Masking of internal node logical faults with using the
subcircuit that outputs are connected with circuit C internal nodes that are fed by fault nodes …

In this paper, we propose an automated method for debugging and rectification of logical
bugs in processors that are implemented on FPGAs. Our method is based on preserving the …

Identifying logical relationships among internal/input/output signals is one of the key
analyses for formal verification, logic synthesis, test pattern generation, and others. It is also …

The VLSI CAD flow encompasses an abundance of critical NP-complete and PSPACE-
complete problems. Instead of developing a dedicated algorithm for each, the trend during …

In this work, we first study LUT optimization in PPCs for increasing their area-efficiency for
yield improvement. We focus on the fact that although 2 2n configurations are available for …

In this paper, we present a new technique and its experimental results for solving partial
logic synthesis problems through training a topologically similar binarized neural network …

Here we first introduce Quantified Boolean Formula (QBF) based approaches to logic
synthesis and testing in general including automatic corrections of designs. It is formulated …