SRAM cell design challenges in modern deep sub-micron technologies: An overview

W Gul, M Shams, D Al-Khalili - Micromachines, 2022 - mdpi.com
Microprocessors use static random-access memory (SRAM) cells in the cache memory
design. As a part of the central computing component, their performance is critical. Modern …

A survey on two-dimensional Error Correction Codes applied to fault-tolerant systems

D Freitas, C Marcon, J Silveira, L Naviner… - Microelectronics …, 2022 - Elsevier
The number of memory faults operating in radiation environments increases with the
electronic device miniaturization. One-dimensional (1D) Error Correction Codes (ECCs) are …

Efficient implementations of 4-bit burst error correction for memories

J Li, L Xiao, P Reviriego… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
In recent years, there has been a growing interest in error correction codes (ECCs) that can
correct localized errors in memories. This is due to the larger fraction of radiation induced …

Correction of adjacent errors with low redundant matrix error correction codes

J Gracia-Moran, LJ Saiz-Adalid… - 2018 Eighth Latin …, 2018 - ieeexplore.ieee.org
The continuous growth of the integration scale in CMOS circuits has derived in an increase
in the memory systems capacity, but also in their fault rate. In this way, the probabilities of …

PCoSA: A product error correction code for use in memory devices targeting space applications

D Freitas, D Mota, R Goerl, C Marcon, F Vargas… - Integration, 2020 - Elsevier
The radiation sensitivity of integrated memory cells increases dramatically as the supply
voltage decreases. Although there are some Error Correcting Code (ECC) studies to prevent …

Design and implementation of error detection and correction system for semiconductor memory applications

T Satyanarayana, VA Qureshi, G Divya - 2022 - IET
VLSI RAM chips build memories in all modern computers. Hence, these devices are highly
reliable and can last for decades before a single chip fails. While combining many chips in a …

静态随机存储器在轨自检算法

吴洋, 王羿, 于新宇, 许智龙, 任放… - 北京航空航天大学学报, 2021 - bhxb.buaa.edu.cn
静态随机存储器(SRAM) 在轨自检应用于星载电子设备上电初始化过程中, 能够在电子设备开始
工作前发现存储器的故障单元, 为评估电子设备健康状态提供依据. 分析了SRAM …

SET Tolerable SRAM Hardened by DMR Circuit With Feedback-Split-Gate Voter and High-Speed Hierarchical Structure

Y Han, X Cheng, X Xue, J Han, J Xu… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
The scaled process technology and the increased operational frequency deteriorated the
stability of the Static Random-Access Memory (SRAM) working in the harsh radiation …

Multi-bit low redundancy error control with parity sharing for NoC interconnects

US Himaja, M Vinodhini… - 2018 3rd International …, 2018 - ieeexplore.ieee.org
Network-on-Chips (NoCs) have become an efficient solution to overcome the issues of the
bus-based architectures in System-on-Chips (SoCs). In the era of deep sub-micron …

New decoding techniques for modified product code used in critical applications

DCC Freitas, C Marcon, JAN Silveira… - Microelectronics …, 2022 - Elsevier
The shrinking of memory devices increased the probability of system failures due to the
higher sensitivity to electromagnetic radiation. Critical memory systems employ fault-tolerant …