Gap-free Processor Verification by S2QED and Property Generation

K Devarajegowda, MR Fadiheh, E Singh… - … , Automation & Test …, 2020 - ieeexplore.ieee.org
The required manual effort and verification expertise are among the main hurdles for
adopting formal verification in processor design flows. Developing a set of properties that …

Isa modeling with trace notation for context free property generation

K Devarajegowda, E Kaja, S Prebeck… - 2021 58th ACM/IEEE …, 2021 - ieeexplore.ieee.org
The scalable and extendable RISC-V ISA introduced a new level of flexibility in designing
highly customizable processors. This flexibility in processor designs adds to the complexity …

[PDF][PDF] Formal fault propagation analysis that scales to modern automotive SoCs

S Marchese, J Grosse - 2017 Design and Verification …, 2017 - dvcon-proceedings.org
Modern automotive Systems-On-Chip (SoCs) implement numerous safety-critical functions.
Random hardware faults, eg single event latch-ups, may cause errors in circuit behavior and …

Exploiting hardware unobservability for low-power design and safety analysis in formal verification-driven design flows

S Udupi, J Urdahl, D Stoffel… - IEEE Transactions on Very …, 2019 - ieeexplore.ieee.org
Formal techniques for the functional verification of System-on-Chip (SoC) hardware have
matured significantly over the last years. They can penetrate deeply into a design to exhibit …

On Hardware Verification In An Open Source Context

B Marshall - Workshop on Open Source Design …, 2019 - research-information.bris.ac.uk
The last few decades have seen the complexity of commercial hardware designs increase
by multiple orders of magnitude. This has driven corresponding increases in commercial tool …

[PDF][PDF] Model-based Generation of Assertions for Pre-silicon Verification

K Devarajegowda - 2021 - kluedo.ub.rptu.de
An important milestone in the history of semiconductors is the invention of a point-contact
transistor in 1947 by John Bardeen and Walter Brattain of Bell Laboratories. In the following …

Automated verification of a System-on-Chip for radiation protection fulfilling Safety Integrity Level 2

K Ceesay-Seitz - 2019 - cds.cern.ch
Abstract The new CERN Radiation MOnitoring Electronics (CROME) system is currently
being devel-oped at CERN. It consists of hundreds of units, which measure ionizing …

[图书][B] Entwicklung von Methoden zur abstrakten Modellierung von Automotive Systems-on-Chips

A Kirchner - 2022 - library.oapen.org
Abstract Diese Open-Access-Publikation bietet zu Beginn einen Einblick in die Grundlagen
der modellbasierten Systementwicklung. Dabei analysiert die Publikation aktuell …

Fault detection and diagnostic coverage for the domain control units of vehicle E/E systems on functional safety

KB Yeon, DH Lee - 2017 20th International Conference on …, 2017 - ieeexplore.ieee.org
This paper deals with the method of a fault detection and diagnostic system for the domain
control units and the garnish systems, a vehicle equipped with advanced vehicle E/E …