The present disclosure is directed to digital phase-locked loops (DPLLs) and hybrid phase-
locked loops (HPLL) for establishing and maintaining a phase relationship between a …

H03M1/0634—Continuously compensating for, or preventing, undesired influence of
physical parameters characterised by the use of methods or means not specific to a …

BACKGROUND Current solutions for ADPLLs may use a time interval to adjust various lock
states. During this settling time, distur bances in both phase and frequency may occur …

BACKGROUND An all-digital phase locked loop (ADPLL) is a circuit that locks the phase of
a local oscillator clock signal, output from the ADPLL, to the phase of a frequency reference …

(57) ABSTRACT A fully integrated feedback controlled coil driver is dis closed for inductive
power transfer to electronic devices. For efficient power transfer, a Voltage across a Switch …

Abstract A digital PLL (DPLL) includes a time-to-digital converter (TDC) and a control unit.
The TDC is periodically enabled for a short duration to quantize phase information and …

A digital phase-locked loop includes a digital loop filter, a digitally controllable oscillator
(DCO), and an injection-locked calibration-free time-to-digital converter (TDC) having a ring …

(57) ABSTRACT A hybrid analog/digital control approach for a digitally controlled oscillator
augments a digital control path with an analog control path that acts to center the digital …

US10177941B2 - Method and apparatus for estimating and correcting phase error in
wireless communication system - Google Patents US10177941B2 - Method and apparatus …

A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an
example, of the present disclosure operates in a frequency tracking mode to adjust a …