Efficient path profiling
A path profile determines how many times each acyclic path in a routine executes. This type
of profiling subsumes the more common basic block and edge profiling, which only …
of profiling subsumes the more common basic block and edge profiling, which only …
[图书][B] Reliability, Availability and Serviceability of Networks-on-chip
É Cota, A de Morais Amory, MS Lubaszewski - 2011 - books.google.com
This book presents an overview of the issues related to the test, diagnosis and fault-
tolerance of Network on Chip-based systems. It is the first book dedicated to the quality …
tolerance of Network on Chip-based systems. It is the first book dedicated to the quality …
A fully-asynchronous low-power framework for GALS NoC integration
Y Thonnart, P Vivet, F Clermidy - 2010 Design, Automation & …, 2010 - ieeexplore.ieee.org
Requiring more bandwidth at reasonable power consumption, new communication
infrastructures must provide adequate solutions to guarantee performance during physical …
infrastructures must provide adequate solutions to guarantee performance during physical …
Efficient design-for-test approach for networks-on-chip
To achieve high reliability in on-chip networks, it is necessary to test the network
continuously with Built-in Self-Tests (BIST) so that the faults can be detected quickly and the …
continuously with Built-in Self-Tests (BIST) so that the faults can be detected quickly and the …
TSV-OCT: A scalable online multiple-TSV defects localization for real-time 3-D-IC systems
In order to detect and localize through-silicon-via (TSV) failures in both manufacturing and
operating phases, most of the existing methods use a dedicated testing mechanism with …
operating phases, most of the existing methods use a dedicated testing mechanism with …
A reconfigurable source-synchronous on-chip network for GALS many-core platforms
This paper presents a globally-asynchronous locally-synchronous (GALS)-compatible circuit-
switched on-chip network that is well suited for use in many-core platforms targeting …
switched on-chip network that is well suited for use in many-core platforms targeting …
Non-blocking testing for network-on-chip
To achieve high reliability in on-chip networks, it is necessary to test the network as
frequently as possible to detect physical failures before they lead to system-level failures. A …
frequently as possible to detect physical failures before they lead to system-level failures. A …
Design of fault-tolerant and reliable networks-on-chip
Networks-on-Chips (NoCs) are at the core of high performance multi-processor systems-on-
chips. As the number of cores and sub-systems on chip grows, the size and complexity of …
chips. As the number of cores and sub-systems on chip grows, the size and complexity of …
A novel asynchronous first-in-first-out adapting to multi-synchronous network-on-chips
The integration of a variety of IP cores into a single chip to meet the high demand of new
applications leads to many challenges in timing issues, especially the interface between …
applications leads to many challenges in timing issues, especially the interface between …
[PDF][PDF] FPGA implementation of a low latency and high throughput network-on-chip router architecture
The Network-on-Chip (NoC) paradigm has recently been known as a promising solution for
designing large complex Systems-on-Chip (SoCs), especially when the semiconductor …
designing large complex Systems-on-Chip (SoCs), especially when the semiconductor …