Accuracy of CMOS-based piezoresistive stress sensor for engineering applications of thermal loading condition: Theoretical review and experimental validation
A Prisacaru, A Palczynska, P Gromala… - IEEE Sensors …, 2019 - ieeexplore.ieee.org
Measurement uncertainties of a CMOS-based piezoresistive stress sensor are studied for
low cycle thermal loading applications. After the fundamentals of the sensor are reviewed …
low cycle thermal loading applications. After the fundamentals of the sensor are reviewed …
Hybrid smart temperature compensation system for piezoresistive 3D stress sensors
This paper proposes a new hybrid temperature compensation system for doped silicon-
based piezoresistive 3D stress sensors. The developed compensation system integrates a …
based piezoresistive 3D stress sensors. The developed compensation system integrates a …
Microfabrication and calibration of a single-polarity piezoresistive three-dimensional stress sensing chip
HH Gharib, WA Moussa - Journal of Micromechanics and …, 2013 - iopscience.iop.org
A single-polarity (n-type) piezoresistive sensing chip for three-dimensional (3D) stress
sensing has been microfabricated and fully calibrated. The sensing chip, which is capable of …
sensing has been microfabricated and fully calibrated. The sensing chip, which is capable of …
A smart high accuracy calibration algorithm for 3-D piezoresistive stress sensor
MO Kayed, AA Balbola, WA Moussa - IEEE Sensors Journal, 2016 - ieeexplore.ieee.org
Numerical and experimental sensitivity analyses in this paper indicate that the accuracy of a
silicon multi-element piezoresistive (PR) stress sensor can be dramatically influenced by the …
silicon multi-element piezoresistive (PR) stress sensor can be dramatically influenced by the …
In-situ strain measurement with metallic thin film sensors
C Taylor, SK Sitaraman - 2012 IEEE 62nd Electronic …, 2012 - ieeexplore.ieee.org
With increasing importance of 3D packaging systems, more and more dies will be stacked
on top of each other and connected using through silicon vias (TSVs) and solder bumps. In …
on top of each other and connected using through silicon vias (TSVs) and solder bumps. In …
Thermo-mechanical characterization of passive stress sensors in Si interposer
B Vianne, P Bar, V Fiori… - … and Mulit-Physics …, 2014 - ieeexplore.ieee.org
Passive stress sensors have been integrated in a silicon interposer test vehicle to
investigate thermo-mechanical stress in a typical 2.5 D system. The present sensors are …
investigate thermo-mechanical stress in a typical 2.5 D system. The present sensors are …
Application of silicon stress sensor in flip chip packaging system
C Jiang, F Xiao, H Yang, C Dou - 2011 12th International …, 2011 - ieeexplore.ieee.org
Flip chip packaging system consists of different materials in the connecting parts, and has an
undesirable stress distribution on the chips. Large residual strain will lead to a deterioration …
undesirable stress distribution on the chips. Large residual strain will lead to a deterioration …
[图书][B] An Investigation of Using n-Si Piezoresistive Behavior to Develop a Three-Dimensional Stress Sensing Rosette
HMH Gharib - 2013 - search.proquest.com
This work involves the design, microfabrication, calibration, and testing of a new silicon-
based piezoresistive rosette capable of extracting the three-dimensional (3D) stresses in the …
based piezoresistive rosette capable of extracting the three-dimensional (3D) stresses in the …
[PDF][PDF] Prognostics and health monitoring for ECU based on piezoresistive sensor measurements
A Palczynska - 2018 - tuprints.ulb.tu-darmstadt.de
This dissertation presents a new approach to prognostics and health monitoring for
automotive applications using a piezoresistive silicon stress sensor. The stress sensor is a …
automotive applications using a piezoresistive silicon stress sensor. The stress sensor is a …
Research on the stress in stacked chip packages
C Jiang, J Xi, F Xiao, C Dou… - 2013 14th International …, 2013 - ieeexplore.ieee.org
Stacked chip packaging (3D packaging) is an effective method to increase the density of
electronic packaging, due to the packaging density on an single chip has reached the limit of …
electronic packaging, due to the packaging density on an single chip has reached the limit of …