Forward error correction for 100 G transport networks
F Chang, K Onohara, T Mizuochi - IEEE Communications …, 2010 - ieeexplore.ieee.org
The role of forward error correction has become of critical importance in fiber optic
communications, as backbone networks increase in speed to 40 and 100 Gb/s, particularly …
communications, as backbone networks increase in speed to 40 and 100 Gb/s, particularly …
On advanced FEC and coded modulation for ultra-high-speed optical transmission
IB Djordjevic - IEEE Communications Surveys & Tutorials, 2016 - ieeexplore.ieee.org
This tutorial paper presents an overview of advanced FEC and coded modulation (CM) for
optical communications. It describes the following ultra-high-speed optical transport …
optical communications. It describes the following ultra-high-speed optical transport …
An efficient 10GBASE-T ethernet LDPC decoder design with low error floors
Z Zhang, V Anantharam… - IEEE Journal of Solid …, 2010 - ieeexplore.ieee.org
A grouped-parallel low-density parity-check (LDPC) decoder is designed for the (2048,
1723) Reed-Solomon-based LDPC (RS-LDPC) code suitable for 10GBASE-T Ethernet. A …
1723) Reed-Solomon-based LDPC (RS-LDPC) code suitable for 10GBASE-T Ethernet. A …
End-to-end energy modeling and analysis of long-haul coherent transmission systems
In this paper, we model and analyze the end-to-end energy consumption of 100-Gbps
coherent long-haul transmission systems. In particular, we investigate the impact of forward …
coherent long-haul transmission systems. In particular, we investigate the impact of forward …
FPGA verification of a single QC-LDPC code for 100 Gb/s optical systems without error floor down to BER of 10−15
FPGA verification of a single QC-LDPC code for 100 Gb/s optical systems without error floor
down to BER of 10<sup> Page 1 FPGA Verification of a Single QC-LDPC Code for 100 …
down to BER of 10<sup> Page 1 FPGA Verification of a Single QC-LDPC Code for 100 …
Majority-based tracking forecast memories for stochastic LDPC decoding
SS Tehrani, A Naderi, GA Kamendje… - IEEE Transactions …, 2010 - ieeexplore.ieee.org
This paper proposes majority-based tracking forecast memories (MTFMs) for area efficient
high throughput ASIC implementation of stochastic Low-Density Parity-Check (LDPC) …
high throughput ASIC implementation of stochastic Low-Density Parity-Check (LDPC) …
Finite alphabet iterative decoders—Part I: Decoding beyond belief propagation on the binary symmetric channel
SK Planjery, D Declercq, L Danjean… - IEEE Transactions on …, 2013 - ieeexplore.ieee.org
We introduce a new paradigm for finite precision iterative decoding on low-density parity-
check codes over the binary symmetric channel. The messages take values from a finite …
check codes over the binary symmetric channel. The messages take values from a finite …
Design of LDPC decoders for improved low error rate performance: quantization and algorithm choices
Many classes of high-performance low-density parity-check (LDPC) codes are based on
parity check matrices composed of permutation submatrices. We describe the design of a …
parity check matrices composed of permutation submatrices. We describe the design of a …
Cyclic and quasi-cyclic LDPC codes on constrained parity-check matrices and their trapping sets
This paper is concerned with construction and structural analysis of both cyclic and quasi-
cyclic codes, particularly low-density parity-check (LDPC) codes. It consists of three parts …
cyclic codes, particularly low-density parity-check (LDPC) codes. It consists of three parts …
[图书][B] LDPC code designs, constructions, and unification
Written by leading experts, this self-contained text provides systematic coverage of LDPC
codes and their construction techniques, unifying both algebraic-and graph-based …
codes and their construction techniques, unifying both algebraic-and graph-based …