Addressing the challenges of extreme scale computing requires holistic design of new
programming models and systems that support those models. This paper discusses the …

Conventional oblivious routing algorithms are either not application-aware or assume that
each flow has its own private channel to ensure deadlock avoidance. We present a …

We present DARSIM, a parallel, highly configurable, cycle-level network-on-chip simulator
based on an ingress-queued wormhole router architecture. The parallel simulation engine …

We present hornet, a parallel, highly configurable, cycle-level multicore simulator based on
an ingress-queued wormhole router network-on-chip (NoC) architecture. The parallel …

A bidirectional channel network-on-chip (BiNoC) architecture is proposed to enhance the
performance of on-chip communication. In a BiNoC, each communication channel allows to …

A novel Bidirectional Fault-Tolerant NoC (BFT-NoC) architecture capable of mitigating both
static and dynamic channel failures is proposed. In a traditional NoC platform, a faulty data …

We present HORNET, a parallel, highly configurable, cycle-level multicore simulator based
on an ingress-queued worm-hole router NoC architecture. The parallel simulation engine …

Networks-on-Chip (NoC) serve as efficient and scalable communication substrates for many-
core architectures. Currently, the bandwidth provided in NoCs is over provisioned for their …

Network-on-Chips (NoCs) are quickly becoming the standard communication paradigm for
the growing number of cores on the chip. While NoCs can deliver sufficient bandwidth and …

In this paper, we propose a flexible NoC architecture and a dynamic distributed routing
algorithm which can enhance the NoC communication performance with minimal energy …