[PDF][PDF] Implementing SOS with active objects: A case study of a multicore memory system
This paper describes the development of a parallel simulator of a multicore memory system
from a model formalized as a structural operational semantics (SOS). Our implementation …
from a model formalized as a structural operational semantics (SOS). Our implementation …
Proving correctness of parallel implementations of transition system models
F de Boer, EB Johnsen, VKI Pun… - ACM Transactions on …, 2024 - dl.acm.org
This article addresses the long-standing problem of program correctness for programs that
describe systems of parallel executing processes. We propose a new method for proving …
describe systems of parallel executing processes. We propose a new method for proving …
[HTML][HTML] A formal model of data access for multicore architectures with multilevel caches
The performance of software running on parallel or distributed architectures can be severely
affected by the location of data. In shared memory multicore architectures, data movement …
affected by the location of data. In shared memory multicore architectures, data movement …
Proving Correctness of Parallel Implementations of Transition System Specifications
FS de Boer, EB Johnsen, VKI Pun… - arXiv preprint arXiv …, 2023 - arxiv.org
The overall problem addressed in this paper is the long-standing problem of program
correctness, and in particular programs that describe systems of parallel executing …
correctness, and in particular programs that describe systems of parallel executing …
Deployment by construction for multicore architectures
In stepwise program development, abstract specifications can be transformed into (parallel)
programs which preserve functional correctness. Although tackling bad performance after a …
programs which preserve functional correctness. Although tackling bad performance after a …
Leveraging access mode declarations in a model for memory consistency in heterogeneous systems
On a system that exposes disjoint memory spaces to the software, a program has to address
memory consistency issues and perform data transfers so that it always accesses valid data …
memory consistency issues and perform data transfers so that it always accesses valid data …
FPGA Implementation of Snoopy Bus based Cache Coherence Protocols for Dual Processor System.
S Navya, YP Sai, KS Reddy - Turkish Online Journal of …, 2021 - search.ebscohost.com
Abstract When designing of Shared Memory Multiprocessor systems Cache Coherence
becomes the great challenge to deal because incoherence may occur when the processors …
becomes the great challenge to deal because incoherence may occur when the processors …
[引用][C] Technical Report: A Formal Model of Parallel Execution on Multicore Architectures with Multilevel Caches Shiji Bijo
EB Johnsen, KI Pun, SLT Tarifa
[引用][C] Technical Report: Modelling Data Access Patterns with Atomic Sections for Multicore Architectures
S Bijo, KI Pun, SLT Tarifa - 2017