Aggressive storage density scaling in modern main memories causes increasing error rates
that are addressed using error-mitigation techniques. State-of-the-art techniques for …

Error-correcting code (ECC) has been widely used in DRAM-based memory systems to
address the exacerbating random errors following the fabrication process scaling. However …

This paper provides a comprehensive overview of the security vulnerability known as
rowhammer in Dynamic Random-Access Memory (DRAM). While DRAM offers many …

Generational improvements to commodity DRAM throughout half a century have long
solidified its prevalence as main memory across the computing industry. However …

Improvements in main memory storage density are primarily driven by process technology
scaling, which negatively impacts reliability by exacerbating various circuit-level error …

Several circuit components can induce bit errors at high-speed wireline interfaces. Hence,
accurate identification and correction of error points in various circuits using straightforward …

Multi-bit error and downtime due to uncorrectable error (UE) in a dual in line memory
module (DIMM) have received great attention in data centers for its high repair or …

Dynamic random-access memory (DRAM) is crucial for high-performance computing due to
its speed and storage capacity. As the demand for high-capacity memory increases, DRAM …

DRAM manufacturers have started adopting on-die error correcting coding (ECC) to deal
with increasing error rates. The typical single error correcting (SEC) ECC on the memory die …

The reliability of memory subsystems is worsening rapidly and needs to be considered as
one of the primary design objectives when designing today's computer systems. From on …