Design and performance analysis of 6T SRAM cell on different CMOS technologies with stability characterization

S Saun, H Kumar - IOP conference series: materials science and …, 2019 - iopscience.iop.org
With the advent of portable devices, the demand for static random-access memory (SRAM)
is increasing with large use of SRAM in System on Chip and high-performance VLSI circuits …

Machine-learning-based compact modeling for sub-3-nm-node emerging transistors

SM Woo, HJ Jeong, JY Choi, HM Cho, JT Kong… - Electronics, 2022 - mdpi.com
In this paper, we present an artificial neural network (ANN)-based compact model to
evaluate the characteristics of a nanosheet field-effect transistor (NSFET), which has been …

A variation-aware design for storage cells using Schottky-barrier-type GNRFETs

E Abbasian, M Gholipour - Journal of Computational Electronics, 2020 - Springer
Graphene nanoribbons (GNRs) are a good replacement material for silicon to overcome
short-channel effects in nanoscale devices. However, with continuous technology scaling …

Speed Improvement in SRAM Cell Using Transmission Gates

P Swetha, PS Meghana, J Charisma… - … , Electrical Circuits and …, 2020 - ieeexplore.ieee.org
All battery-operated devices require primary memory that responds fast. By virtue of its high
speed and performance, Static RAM is commonly used as cache memory and main memory …

Low power, high-performance reversible logic enabled CNTFET SRAM cell with improved stability

H Kumar, S Srivastava, B Singh - Materials Today: Proceedings, 2021 - Elsevier
With aggressive scaling of device feature size, performance of conventional MOS SRAM is
affected and reliability, leakage power dissipation, and testing related issues arise due to …

Design and Performance Analysis of 1‐Bit FinFET Full Adder Cells for Subthreshold Region at 16 nm Process Technology

A Abdul Tahrim, HC Chin, CS Lim… - Journal of …, 2015 - Wiley Online Library
The scaling process of the conventional 2D‐planar metal‐oxide semiconductor field‐effect
transistor (MOSFET) is now approaching its limit as technology has reached below 20 nm …

Design and Performance Evaluation of Energy Efficient 8-Bit ALU at Ultra-Low Supply Voltages Using FinFET with 20 nm Technology

V Vijay, PC Shekar, S Sadulla, P Manoja… - VLSI Architecture for …, 2022 - taylorfrancis.com
In the last few years, the tiny size of MOSFET (ie, less than tens of nano-meters) created
some operational problems such as increased gate-oxide leakage, amplified junction …

Variability aware FinFET SRAM cell with improved stability and power for low power applications

S Birla - Circuit World, 2019 - emerald.com
Purpose Major area of a die is consumed in memory components. Almost 60-70% of chip
area is being consumed by “Memory Circuits”. The dominant memory in this market is …

A dual port 8T SRAM cell using FinFET & CMOS logic for leakage reduction and enhanced read & write stability

C Duari, S Birla, AK Singh - Journal of Integrated Circuits and Systems, 2020 - jics.org.br
Abstract Static Random-Access Memory cells with ultralow leakage and superior stability are
the primary choice of embedded memories in contemporary smart devices. This paper …

Proposal and Analysis of a High Read and Write Noise Margin 6T-SRAM Cell Using Novel Core Insulator Double-Gate (CIDG) MOSFETs

S Jaiswal, SK Gupta - Journal of Electronic Materials, 2024 - Springer
Static random-access memory (SRAM) is in great demand due to the development of
portable electronics and its growing popularity in system-on-chip and advanced very-large …