Clock and phase alignment between physical layers and controller
SI Azad, B Chau, T Knopp - US Patent 11,581,881, 2023 - Google Patents
US11581881B1 - Clock and phase alignment between physical layers and controller - Google
Patents US11581881B1 - Clock and phase alignment between physical layers and controller …
Patents US11581881B1 - Clock and phase alignment between physical layers and controller …
Apparatus and methods for clock duty cycle correction and deskew
WH Chen - US Patent 11,579,649, 2023 - Google Patents
Apparatus and methods for clock duty cycle correction and deskew are provided. In certain
embodiments, a clock distribution circuit includes a clock driver that provides a differential …
embodiments, a clock distribution circuit includes a clock driver that provides a differential …
Digital loop filter of low latency and low operation and clock data recovery circuit including the same
J Lee, KIM Sunggeun, H Lee, SON Seuk… - US Patent …, 2024 - Google Patents
A clock data recovery circuit includes a bang bang phase detector receiving data and a
clock signal and determining whether a phase of the clock signal leads or lags a phase of …
clock signal and determining whether a phase of the clock signal leads or lags a phase of …
Apparatus and methods for low power frequency clock generation and distribution
2020-12-01 Assigned to CIENA CORPORATION reassignment CIENA CORPORATION
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …