A closer look at spatiotemporal convolutions for action recognition

D Tran, H Wang, L Torresani, J Ray… - Proceedings of the …, 2018 - openaccess.thecvf.com
In this paper we discuss several forms of spatiotemporal convolutions for video analysis and
study their effects on action recognition. Our motivation stems from the observation that 2D …

OSCAR: Orchestrating STT-RAM cache traffic for heterogeneous CPU-GPU architectures

J Zhan, O Kayıran, GH Loh, CR Das… - 2016 49th annual IEEE …, 2016 - ieeexplore.ieee.org
As we integrate data-parallel GPUs with general-purpose CPUs on a single chip, the
enormous cache traffic generated by GPUs will not only exhaust the limited cache capacity …

Contemporary CMOS aging mitigation techniques: Survey, taxonomy, and methods

N Khoshavi, RA Ashraf, RF DeMara, S Kiamehr… - Integration, 2017 - Elsevier
The proposed paper addresses the overarching reliability issue of transistor aging in
nanometer-scaled circuits. Specifically, a comprehensive survey and taxonomy of …

Performance/reliability-aware resource management for many-cores in dark silicon era

MH Haghbayan, A Miele, AM Rahmani… - IEEE Transactions …, 2017 - ieeexplore.ieee.org
Aggressive technology scaling has enabled the fabrication of many-core architectures while
triggering challenges such as limited power budget and increased reliability issues, like …

A lifetime-aware runtime mapping approach for many-core systems in the dark silicon era

MH Haghbayan, A Miele, AM Rahmani… - … , Automation & Test …, 2016 - ieeexplore.ieee.org
In this paper, we propose a novel lifetime reliability-aware resource management approach
for many-core architectures. The approach is based on hierarchical architecture, composed …

Aging-aware workload management on embedded gpu under process variation

H Lee, M Shafique… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
Graphics Processing Units (GPUs) have been employed in embedded systems to handle
increased amounts of computation and to satisfy the timing requirement. Due to the small …

Aging-aware boosting

H Khdr, H Amrouch, J Henkel - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
DVFS-based boosting techniques have been widely employed by commercial multi-core
processors, due to their superiority in improving the performance. Boosting, however, is …

Run-time Resource Management in CMPs Handling Multiple Aging Mechanisms

H Haghbayan, A Miele, O Mutlu… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
Run-time resource management is fundamental for efficient execution of workloads on Chip
Multiprocessors. Application-and system-level requirements (eg, on performance versus …

Trends in on-chip dynamic resource management

K Moazzemi, A Kanduri, D Juhász… - 2018 21st Euromicro …, 2018 - ieeexplore.ieee.org
The Complexity of emerging multi/many-core architectures and diversity of modern
workloads demands coordinated dynamic resource management methods. We introduce a …

Performance constraint-aware task mapping to optimize lifetime reliability of manycore systems

V Rathore, V Chaturvedi, T Srikanthan - … of the 26th edition on Great …, 2016 - dl.acm.org
Negative bias temperature instability (NBTI) has emerged as a critical challenge to lifetime
reliability of computing systems. Traditionally, temperature-aware methodologies are used to …