Performance Enhancement in Machine learning Algorithm using FinFET Technology

A Haldorai, RB Lincy, M Suriya… - 2024 5th International …, 2024 - ieeexplore.ieee.org
The present machine learning classifiers utilizes digital MOSFETS circuits, which consumes
lot of power for its processing. To overcome the mentioned issue, Mixed-signal machine …

Design and Analysis of RNS based Montgomery multiplier using FinFET Technology

EE Nithila - 2024 IEEE 9th International Conference for …, 2024 - ieeexplore.ieee.org
This article describes the design and analysis of RNS based Montgomery multiplier. The
proposed design harness FinFET technology for low power and delay applications …

Design and FPGA implementation of recursive multiplier using approximated 4: 2 compressor

V Prabhu, V Karthik, MR Prasath… - AIP Conference …, 2024 - pubs.aip.org
Using an estimated 4: 2 compressor, we develop a recursive multiplier in this article. To
reduce power consumption, latency, and space requirements without compromising …

Inter-Vehicular Communication Using Split Ring Resonator

S Ashok, S Palanivel, P Prasanth… - … on Intelligent and …, 2024 - ieeexplore.ieee.org
For any wireless communication system, having an antenna is essential. However, it can be
challenging to evaluate them, especially when developing new technology for intelligent …

[PDF][PDF] Content Addressable Memory performance Analysis using NAND Structure FinFET

R Bhuvana, V Prabhu, PG Kuppusamy… - Global Journal of Pure …, 2016 - researchgate.net
In the recent past, scaling in Complementary metal-oxide semiconductor (CMOS)
technology has faced a bout of challenges such as the decrease in gate control, high power …

[PDF][PDF] Design of arithmetic unit using 32-Nm CNFET technology

R Babithalincy, P Sharmila, R Kalpana… - International Journal of …, 2016 - academia.edu
The main aims of the electronic manufacturing are miniaturization and make small size
products. Recently we are using carbon nano tube field effect transistor (CNFET), which has …

Implementation of 12 Bit R-2R DAC Using Cadence (90nm)

K Saravanan, S Tamilmani, SD Surendar… - International Journal of … - neliti.com
Abstract An R-2R DAC utilizes less special esteem which is in contrast with to the binary
weighed-input DAC. Continuous sampling and measuring of an analog signal occurs over …

[PDF][PDF] High Speed Pipeline Architecture Using Mixture of Domino Logic Gates

A Subasri, BG Gopal… - Global Journal of Pure …, 2016 - researchgate.net
The present study aims to design method of asynchronous logic pipeline which focuses on
improving the quality of the circuit efficient and it is used for a wide range of applications …