A 28-nm 75-fsrms Analog Fractional- Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle …
W Wu, CW Yao, K Godbole, R Ni… - IEEE Journal of Solid …, 2019 - ieeexplore.ieee.org
An analog fractional-sampling phase-locked loop (PLL) is presented. It achieves 75-fs rms
jitter, integrated from 10 kHz to 10 MHz, and a− 249.7-dB figure of merit (FoM) at the …
jitter, integrated from 10 kHz to 10 MHz, and a− 249.7-dB figure of merit (FoM) at the …
16.5 A Fractional-N Synthesizer with 110fsrms Jitter and a Reference Quadrupler for Wideband 802.11ax
F Song, Y Zhao, B Wu, L Tang, L Lin… - … Solid-State Circuits …, 2019 - ieeexplore.ieee.org
The next-generation 802.11 ax WLAN standard improves the throughput by supporting 1024-
QAM in a channel bandwidth of 160MHz, demanding extremely low jitter values for the …
QAM in a channel bandwidth of 160MHz, demanding extremely low jitter values for the …
A 2.2-GHz 3.2-mW DTC-Free Sampling Fractional- PLL With −110-dBc/Hz In-Band Phase Noise and −246-dB FoM and −83-dBc Reference Spur
This paper presents the first sampling ΔΣ fractional-N phase-locked loop (PLL) without a
digital-to-time converter (DTC), whose design is challenging and requires complex …
digital-to-time converter (DTC), whose design is challenging and requires complex …
Design high frequency phase locked loop using single ended VCO for high speed applications
The requirement for rapid, reliable computing has grown as the semiconductor industry has
progressed and the process technology has scaled. The demand for high-processing, low …
progressed and the process technology has scaled. The demand for high-processing, low …
A 14-nm low-cost IF transceiver IC with low-jitter LO and flexible calibration architecture for 5G FR2 mobile applications
W Wu, J Lee, PK Lau, T Kang, KK Lau… - 2023 IEEE Radio …, 2023 - ieeexplore.ieee.org
We present a low-cost dual-stream IF transceiver IC (IFIC) for 5G mm-wave mobile
applications. It up/down-converts the baseband signal to an intermediate frequency of 8.4 …
applications. It up/down-converts the baseband signal to an intermediate frequency of 8.4 …
Analysis and Prejudgment of Entire-Link Rejection Ratio of a Spaceborne Microwave Receiver Against Switched Mode Power Supply Harmonics
B Li, G Wan, B Zhao, G Chen, Z Li… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
With the wide application of high-sensitivity broadband microwave receivers, the
requirement of power-supply modulation ratio in receivers is greatly increased. Especially …
requirement of power-supply modulation ratio in receivers is greatly increased. Especially …
Jitter suppression techniques for high-speed sample-and-hold circuits
S Jamali-Zavareh, R Harjani - IEEE Transactions on Circuits …, 2019 - ieeexplore.ieee.org
In this paper, we discuss the limitations of the existing clock jitter reduction techniques, and
introduce ΔΣ sampling, which can reduce the jitter-induced sampling error significantly. We …
introduce ΔΣ sampling, which can reduce the jitter-induced sampling error significantly. We …
Design and Performance Analysis of A Low Power, Low Noise 1.6 GHz Charge Pump Integer-N PLL in Different PVT Corners
SMM Ahsan, T Hassan, SI Hasan… - … on Electrical and …, 2020 - ieeexplore.ieee.org
A fast locking low phase noise 1.6 GHz PLL has been presented in this paper. The PLL was
designed in 28nm technology with 1V nominal supply voltage. The phase noise of the PLL …
designed in 28nm technology with 1V nominal supply voltage. The phase noise of the PLL …
[图书][B] A Quadrature PLL with Novel Charge Pump Architecture
B Pittinsky - 2023 - search.proquest.com
At the heart of any RF communication system is a carrier frequency synthesizer, usually an
analog PLL. This PLL acts as aa phase/frequency amplifier, amplifying an input f ref signal …
analog PLL. This PLL acts as aa phase/frequency amplifier, amplifying an input f ref signal …
Reduction of noise in output clock due to unequal successive time periods of a reference clock in a fractional-N phase locked loop
S Sasi, H Reddy - US Patent 11,658,667, 2023 - Google Patents
H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of
the loop the oscillator being a digital oscillator, eg composed of a fixed oscillator followed by …
the loop the oscillator being a digital oscillator, eg composed of a fixed oscillator followed by …