In high performance processors, the design of on-chip memory hierarchies is crucial for
performance and energy efficiency. Current processors rely on large shared Non-Uniform …

Snoop-based cache coherence protocols perform well in small-scale systems by enabling
low latency cache-to-cache data transfers in just two-hop coherence transactions. However …

The rate of annual data generation grows exponentially. At the same time, there is a high
demand to analyze that information quickly. In the past, every processor generation came …

Shared memory architectures are pervasive in the multicore technology era. Still, sequential
and parallel applications use most of the data as private in a multicore system. Recent …

Sequential and parallel applications use most of the data as private in a multi-core system.
Recent proposals made use of this observation to reduce the area of the coherence …

The end of Dennard scaling has caused a stagnation of the clock frequency in computers.
To overcome this issue, in the last two decades vendors have been integrating larger …

Current large scale systems show increasing power demands, to the point that it has
become a huge strain on facilities and budgets. The increasing restrictions in terms of power …

Hardware errors become more common as silicon technologies shrink and become more
vulnerable, especially in memory cells, which are the most exposed to errors. Permanent …

Following Moore's Law, the number of transistors on chip has been increasing
exponentially, which has led to the increasing complexity of modern processors. As a result …

Example implementations relate to cache coherency protocols as applied to a memory block
range. Exclusive ownership of a range of blocks of memory in a default shared state may be …