CMOS time-to-digital converters for biomedical imaging applications
Time-to-digital converters (TDCs) are high-performance mixed-signal circuits capable of
timestamping events with sub-gate delay resolution. As a result of their high-performance, in …
timestamping events with sub-gate delay resolution. As a result of their high-performance, in …
A 7 bit, 3.75 ps resolution two-step time-to-digital converter in 65 nm CMOS using pulse-train time amplifier
In this paper, a novel pulse-train time amplifier is proposed that achieves linear, accurate,
and programmable gain for a wide input range. Using the proposed pulse-train time …
and programmable gain for a wide input range. Using the proposed pulse-train time …
A 56.4-to-63.4 GHz multi-rate all-digital fractional-N PLL for FMCW radar applications in 65 nm CMOS
W Wu, RB Staszewski, JR Long - IEEE Journal of solid-state …, 2014 - ieeexplore.ieee.org
A mm-wave digital transmitter based on a 60 GHz all-digital phase-locked loop (ADPLL) with
wideband frequency modulation (FM) for FMCW radar applications is proposed. The …
wideband frequency modulation (FM) for FMCW radar applications is proposed. The …
A 9 bit, 1.12 ps resolution 2.5 b/stage pipelined time-to-digital converter in 65 nm CMOS using time-register
In this paper, a 2.5 b/stage pipelined time-to-digital converter (TDC) is presented. For
pipelined operation, a novel time-register is proposed which is capable of storing, adding …
pipelined operation, a novel time-register is proposed which is capable of storing, adding …
A CMOS 76–81-GHz 2-TX 3-RX FMCW radar transceiver based on mixed-mode PLL chirp generator
A fully integrated 76-81-GHz frequency-modulated, continuous-wave (FMCW) radar
transceiver (TRX) in a 65-nm CMOS is presented. Two transmitters (TXs) and three receivers …
transceiver (TRX) in a 65-nm CMOS is presented. Two transmitters (TXs) and three receivers …
A digital phase-locked loop with calibrated coarse and stochastic fine TDC
A Samarah, AC Carusone - IEEE journal of solid-state circuits, 2013 - ieeexplore.ieee.org
A coarse-fine time-to-digital converter (TDC) is presented with a calibrated coarse stage
followed by a stochastic fine stage. On power-up, a calibration algorithm based on a code …
followed by a stochastic fine stage. On power-up, a calibration algorithm based on a code …
An 802.11a/b/g/n Digital Fractional- PLL With Automatic TDC Linearity Calibration for Spur Cancellation
A fractional-N digital phase-locked loop (PLL) architecture with low fractional spur is
presented in this paper. A 2-D Vernier time-to-digital convertor (TDC) is implemented to …
presented in this paper. A 2-D Vernier time-to-digital convertor (TDC) is implemented to …
A 77-GHz mixed-mode FMCW generator based on a Vernier TDC with dual rising-edge fractional-phase detector
A 77-GHz frequency-modulated continuous-wave (FMCW) generator is presented for
millimeter-wave (mm-wave) radar applications. The FMCW chirp is provided by a …
millimeter-wave (mm-wave) radar applications. The FMCW chirp is provided by a …
A 86 MHz–12 GHz digital-intensive PLL for software-defined radios, using a 6 fJ/step TDC in 40 nm digital CMOS
J Borremans, K Vengattaramane… - IEEE Journal of Solid …, 2010 - ieeexplore.ieee.org
A 86 MHz-12 GHz digital-intensive reconfigurable PLL frequency synthesizer is presented
with 100 kHz to 2 MHz bandwidth. It leverages a 6 fJ/step 5.5 ps, 14b coarse-fine TDC and a …
with 100 kHz to 2 MHz bandwidth. It leverages a 6 fJ/step 5.5 ps, 14b coarse-fine TDC and a …
A dither-less all digital PLL for cellular transmitters
L Vercesi, L Fanori, F De Bernardinis… - IEEE Journal of Solid …, 2012 - ieeexplore.ieee.org
An all-digital frequency synthesizer for cellular transmitter is presented. Low phase-noise is
achieved both in-band and out-of-band exploiting a 2-dimensional Vernier time-to-digital …
achieved both in-band and out-of-band exploiting a 2-dimensional Vernier time-to-digital …