Aging-aware logic synthesis
As CMOS technology scales down into the nanometer regime, designers have to add
pessimistic timing margins to the circuit as guardbands to avoid timing violations due to …
pessimistic timing margins to the circuit as guardbands to avoid timing violations due to …
Aging mitigation in memory arrays using self-controlled bit-flipping technique
With CMOS technology downscaling into the nanometer regime, the reliability of SRAM
memories is threatened by accelerated transistor aging mechanisms such as Bias …
memories is threatened by accelerated transistor aging mechanisms such as Bias …
Detecting malicious landing pages in malware distribution networks
Drive-by download attacks attempt to compromise a victim's computer through browser
vulnerabilities. Often they are launched from Malware Distribution Networks (MDNs) …
vulnerabilities. Often they are launched from Malware Distribution Networks (MDNs) …
Stress balancing to mitigate NBTI effects in register files
Negative Bias Temperature Instability (NBTI) is considered one of the major reliability
concerns of transistors in current and upcoming technology nodes and a main cause of their …
concerns of transistors in current and upcoming technology nodes and a main cause of their …
Design of low power SRAM-based ubiquitous sensor for wireless body area networks
K Neeraj, M Mahaboob Basha… - International Journal of …, 2021 - emerald.com
Purpose Smart ubiquitous sensors have been deployed in wireless body area networks to
improve digital health-care services. As the requirement for computing power has drastically …
improve digital health-care services. As the requirement for computing power has drastically …
Evaluating the performance of solvers for integer-linear programming
A Luppold, D Oehlert, H Falk - 2018 - tore.tuhh.de
Optimizing embedded systems often boils down to solving complex combinatorial
optimization problems. Integer-Linear Programming (ILP) turned out to be a powerful tool to …
optimization problems. Integer-Linear Programming (ILP) turned out to be a powerful tool to …
Sizing of the CMOS 6T‐SRAM cell for NBTI ageing mitigation
This study presents a negative bias temperature instability (NBTI) mitigation design
technique for CMOS 6T‐static random access memory (6T‐SRAM) cells. The proposed …
technique for CMOS 6T‐static random access memory (6T‐SRAM) cells. The proposed …
Aging-aware design of microprocessor instruction pipelines
F Oboril, MB Tahoori - … on Computer-Aided Design of Integrated …, 2014 - ieeexplore.ieee.org
As complementary metal-oxide-semiconductor technologies enter nanometer scales,
microprocessors become more vulnerable to transistor aging, mainly due to bias …
microprocessors become more vulnerable to transistor aging, mainly due to bias …
Mitigating BTI-induced degradation in STT-MRAM sensing schemes
Spin-transfer torque magnetic RAM (STT-MRAM), which uses a magnetic tunnel junction to
store binary data, is a promising memory technology. With many benefits, such as low …
store binary data, is a promising memory technology. With many benefits, such as low …
BTI Aging Influence in SRAM-based In-Memory Computing Schemes and its Mitigation
C Dilopoulou, Y Tsiatouhas - 2023 30th IEEE International …, 2023 - ieeexplore.ieee.org
In-Memory Computing (IMC) schemes are constantly gaining interest in the area of Neural
Networks (NN) for performing computations directly in memory, aiming to overcome the data …
Networks (NN) for performing computations directly in memory, aiming to overcome the data …